Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.62	0.00	0.00	94.87				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	516739	8008	0	0
ctrl_rd_A	516739	1297	0	0
host_fifo_config_rd_A	516739	781	0	0
host_nack_handler_timeout_rd_A	516739	759	0	0
host_timeout_ctrl_rd_A	516739	564	0	0
intr_enable_rd_A	516739	3368	0	0
ovrd_rd_A	516739	842	0	0
target_fifo_config_rd_A	516739	964	0	0
target_id_rd_A	516739	1093	0	0
target_timeout_ctrl_rd_A	516739	724	0	0
timeout_ctrl_rd_A	516739	816	0	0
timing0_rd_A	516739	735	0	0
timing1_rd_A	516739	730	0	0
timing2_rd_A	516739	741	0	0
timing3_rd_A	516739	705	0	0
timing4_rd_A	516739	794	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	8008	0	0
T4	2585	12	0	0
T5	13058	3	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	315	0	0
T12	2803	125	0	0
T13	0	19	0	0
T14	0	5	0	0
T15	0	48	0	0
T16	0	521	0	0
T17	0	373	0	0
T19	12449	0	0	0
T22	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	1297	0	0
T2	13674	196	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	5	0	0
T16	0	5	0	0
T17	0	8	0	0
T30	0	40	0	0
T37	0	35	0	0
T50	0	10	0	0
T54	0	11	0	0
T65	0	18	0	0
T66	0	11	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	781	0	0
T2	13674	140	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	17	0	0
T16	0	20	0	0
T17	0	11	0	0
T30	0	9	0	0
T37	0	15	0	0
T50	0	35	0	0
T54	0	6	0	0
T65	0	15	0	0
T66	0	5	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	759	0	0
T2	13674	83	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	23	0	0
T16	0	17	0	0
T17	0	3	0	0
T27	0	2	0	0
T30	0	23	0	0
T37	0	38	0	0
T50	0	33	0	0
T54	0	11	0	0
T65	0	12	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	564	0	0
T2	13674	86	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	8	0	0
T17	0	4	0	0
T30	0	10	0	0
T37	0	20	0	0
T50	0	21	0	0
T65	0	14	0	0
T66	0	2	0	0
T67	0	18	0	0
T68	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	3368	0	0
T1	914	3	0	0
T2	13674	552	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	10	0	0
T8	1531	0	0	0
T9	1646	19	0	0
T10	1049	0	0	0
T14	0	30	0	0
T16	0	5	0	0
T27	0	5	0	0
T37	0	122	0	0
T57	0	7	0	0
T65	0	14	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	842	0	0
T2	13674	130	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T30	0	8	0	0
T37	0	22	0	0
T39	0	8	0	0
T50	0	19	0	0
T54	0	4	0	0
T65	0	11	0	0
T66	0	13	0	0
T67	0	24	0	0
T68	0	17	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	964	0	0
T2	13674	130	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	6	0	0
T16	0	10	0	0
T17	0	11	0	0
T30	0	18	0	0
T37	0	24	0	0
T50	0	9	0	0
T54	0	5	0	0
T65	0	10	0	0
T66	0	7	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	1093	0	0
T2	13674	190	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	22	0	0
T16	0	7	0	0
T17	0	2	0	0
T27	0	1	0	0
T30	0	34	0	0
T37	0	41	0	0
T50	0	10	0	0
T65	0	17	0	0
T66	0	21	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	724	0	0
T2	13674	106	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	2	0	0
T16	0	7	0	0
T17	0	5	0	0
T30	0	11	0	0
T37	0	27	0	0
T50	0	1	0	0
T54	0	8	0	0
T65	0	15	0	0
T66	0	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	816	0	0
T2	13674	111	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	10	0	0
T16	0	13	0	0
T17	0	3	0	0
T27	0	2	0	0
T30	0	19	0	0
T37	0	17	0	0
T50	0	8	0	0
T65	0	12	0	0
T66	0	16	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	735	0	0
T2	13674	139	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	24	0	0
T16	0	9	0	0
T30	0	7	0	0
T37	0	20	0	0
T50	0	18	0	0
T54	0	7	0	0
T65	0	14	0	0
T66	0	12	0	0
T67	0	10	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	730	0	0
T2	13674	99	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	7	0	0
T16	0	10	0	0
T17	0	11	0	0
T30	0	11	0	0
T37	0	17	0	0
T50	0	13	0	0
T65	0	6	0	0
T66	0	12	0	0
T67	0	17	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	741	0	0
T2	13674	133	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	19	0	0
T30	0	10	0	0
T37	0	23	0	0
T39	0	3	0	0
T50	0	14	0	0
T65	0	17	0	0
T66	0	5	0	0
T67	0	26	0	0
T68	0	7	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	705	0	0
T2	13674	131	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	9	0	0
T16	0	4	0	0
T17	0	9	0	0
T27	0	5	0	0
T30	0	20	0	0
T37	0	36	0	0
T65	0	8	0	0
T66	0	1	0	0
T67	0	13	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516739	794	0	0
T2	13674	124	0	0
T3	1705	0	0	0
T4	2585	0	0	0
T5	13058	0	0	0
T6	1492	0	0	0
T7	1480	0	0	0
T8	1531	0	0	0
T9	1646	0	0	0
T10	1049	0	0	0
T11	4454	0	0	0
T14	0	14	0	0
T16	0	11	0	0
T17	0	1	0	0
T30	0	16	0	0
T37	0	17	0	0
T50	0	24	0	0
T65	0	3	0	0
T66	0	2	0	0
T67	0	15	0	0