Module Definition
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Module : i2c_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.85 100.00 99.41 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.85 100.00 99.41 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.85 100.00 99.41 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.84 98.58 98.18 100.00 97.42 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.72 100.00 100.00 94.87 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_acq_fifo_next_data 100.00 100.00
u_acqdata_abyte 100.00 100.00
u_acqdata_signal 100.00 100.00
u_alert_test 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_controller_events_nack 100.00 100.00 100.00 100.00
u_controller_events_unhandled_nack_timeout 88.89 100.00 66.67 100.00
u_ctrl_ack_ctrl_en 100.00 100.00 100.00 100.00
u_ctrl_enablehost 100.00 100.00 100.00 100.00
u_ctrl_enabletarget 100.00 100.00 100.00 100.00
u_ctrl_llpbk 100.00 100.00 100.00 100.00
u_ctrl_nack_addr_after_timeout 100.00 100.00 100.00 100.00
u_fdata0_qe 100.00 100.00 100.00
u_fdata_fbyte 100.00 100.00 100.00 100.00
u_fdata_nakok 100.00 100.00 100.00 100.00
u_fdata_rcont 100.00 100.00 100.00 100.00
u_fdata_readb 100.00 100.00 100.00 100.00
u_fdata_start 100.00 100.00 100.00 100.00
u_fdata_stop 100.00 100.00 100.00 100.00
u_fifo_ctrl0_qe 100.00 100.00 100.00
u_fifo_ctrl_acqrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_fmtrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_rxrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_txrst 100.00 100.00 100.00 100.00
u_host_fifo_config0_qe 100.00 100.00 100.00
u_host_fifo_config_fmt_thresh 100.00 100.00 100.00 100.00
u_host_fifo_config_rx_thresh 100.00 100.00 100.00 100.00
u_host_fifo_status_fmtlvl 100.00 100.00
u_host_fifo_status_rxlvl 100.00 100.00
u_host_nack_handler_timeout_en 100.00 100.00 100.00 100.00
u_host_nack_handler_timeout_val 100.00 100.00 100.00 100.00
u_host_timeout_ctrl 100.00 100.00 100.00 100.00
u_intr_enable_acq_stretch 100.00 100.00 100.00 100.00
u_intr_enable_acq_threshold 100.00 100.00 100.00 100.00
u_intr_enable_cmd_complete 100.00 100.00 100.00 100.00
u_intr_enable_controller_halt 100.00 100.00 100.00 100.00
u_intr_enable_fmt_threshold 100.00 100.00 100.00 100.00
u_intr_enable_host_timeout 100.00 100.00 100.00 100.00
u_intr_enable_rx_overflow 100.00 100.00 100.00 100.00
u_intr_enable_rx_threshold 100.00 100.00 100.00 100.00
u_intr_enable_scl_interference 100.00 100.00 100.00 100.00
u_intr_enable_sda_interference 100.00 100.00 100.00 100.00
u_intr_enable_sda_unstable 100.00 100.00 100.00 100.00
u_intr_enable_stretch_timeout 100.00 100.00 100.00 100.00
u_intr_enable_tx_stretch 100.00 100.00 100.00 100.00
u_intr_enable_tx_threshold 100.00 100.00 100.00 100.00
u_intr_enable_unexp_stop 100.00 100.00 100.00 100.00
u_intr_state_acq_stretch 62.59 77.78 50.00 60.00
u_intr_state_acq_threshold 62.59 77.78 50.00 60.00
u_intr_state_cmd_complete 100.00 100.00 100.00 100.00
u_intr_state_controller_halt 62.59 77.78 50.00 60.00
u_intr_state_fmt_threshold 62.59 77.78 50.00 60.00
u_intr_state_host_timeout 100.00 100.00 100.00 100.00
u_intr_state_rx_overflow 100.00 100.00 100.00 100.00
u_intr_state_rx_threshold 62.59 77.78 50.00 60.00
u_intr_state_scl_interference 100.00 100.00 100.00 100.00
u_intr_state_sda_interference 100.00 100.00 100.00 100.00
u_intr_state_sda_unstable 100.00 100.00 100.00 100.00
u_intr_state_stretch_timeout 100.00 100.00 100.00 100.00
u_intr_state_tx_stretch 62.59 77.78 50.00 60.00
u_intr_state_tx_threshold 62.59 77.78 50.00 60.00
u_intr_state_unexp_stop 100.00 100.00 100.00 100.00
u_intr_test_acq_stretch 100.00 100.00
u_intr_test_acq_threshold 100.00 100.00
u_intr_test_cmd_complete 100.00 100.00
u_intr_test_controller_halt 100.00 100.00
u_intr_test_fmt_threshold 100.00 100.00
u_intr_test_host_timeout 100.00 100.00
u_intr_test_rx_overflow 100.00 100.00
u_intr_test_rx_threshold 100.00 100.00
u_intr_test_scl_interference 100.00 100.00
u_intr_test_sda_interference 100.00 100.00
u_intr_test_sda_unstable 100.00 100.00
u_intr_test_stretch_timeout 100.00 100.00
u_intr_test_tx_stretch 100.00 100.00
u_intr_test_tx_threshold 100.00 100.00
u_intr_test_unexp_stop 100.00 100.00
u_ovrd_sclval 100.00 100.00 100.00 100.00
u_ovrd_sdaval 100.00 100.00 100.00 100.00
u_ovrd_txovrden 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_rdata 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_status_ack_ctrl_stretch 100.00 100.00
u_status_acqempty 100.00 100.00
u_status_acqfull 100.00 100.00
u_status_fmtempty 100.00 100.00
u_status_fmtfull 100.00 100.00
u_status_hostidle 100.00 100.00
u_status_rxempty 100.00 100.00
u_status_rxfull 100.00 100.00
u_status_targetidle 100.00 100.00
u_status_txempty 100.00 100.00
u_status_txfull 100.00 100.00
u_target_ack_ctrl_nack 100.00 100.00
u_target_ack_ctrl_nbytes 100.00 100.00
u_target_fifo_config0_qe 100.00 100.00 100.00
u_target_fifo_config_acq_thresh 100.00 100.00 100.00 100.00
u_target_fifo_config_tx_thresh 100.00 100.00 100.00 100.00
u_target_fifo_config_txrst_on_cond 100.00 100.00 100.00 100.00
u_target_fifo_status_acqlvl 100.00 100.00
u_target_fifo_status_txlvl 100.00 100.00
u_target_id_address0 100.00 100.00 100.00 100.00
u_target_id_address1 100.00 100.00 100.00 100.00
u_target_id_mask0 100.00 100.00 100.00 100.00
u_target_id_mask1 100.00 100.00 100.00 100.00
u_target_nack_count 81.90 100.00 60.00 85.71
u_target_timeout_ctrl_en 100.00 100.00 100.00 100.00
u_target_timeout_ctrl_val 100.00 100.00 100.00 100.00
u_timeout_ctrl_en 100.00 100.00 100.00 100.00
u_timeout_ctrl_val 100.00 100.00 100.00 100.00
u_timing0_thigh 100.00 100.00 100.00 100.00
u_timing0_tlow 100.00 100.00 100.00 100.00
u_timing1_t_f 100.00 100.00 100.00 100.00
u_timing1_t_r 100.00 100.00 100.00 100.00
u_timing2_thd_sta 100.00 100.00 100.00 100.00
u_timing2_tsu_sta 100.00 100.00 100.00 100.00
u_timing3_thd_dat 100.00 100.00 100.00 100.00
u_timing3_tsu_dat 100.00 100.00 100.00 100.00
u_timing4_t_buf 100.00 100.00 100.00 100.00
u_timing4_tsu_sto 100.00 100.00 100.00 100.00
u_txdata 100.00 100.00 100.00 100.00
u_txdata0_qe 100.00 100.00 100.00
u_val_scl_rx 66.67 66.67
u_val_sda_rx 66.67 66.67


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_reg_top
Line No.TotalCoveredPercent
TOTAL353353100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN115311100.00
CONT_ASSIGN116811100.00
CONT_ASSIGN118411100.00
CONT_ASSIGN120011100.00
CONT_ASSIGN121611100.00
CONT_ASSIGN123211100.00
CONT_ASSIGN124811100.00
CONT_ASSIGN126411100.00
CONT_ASSIGN128011100.00
CONT_ASSIGN129611100.00
CONT_ASSIGN131211100.00
CONT_ASSIGN132811100.00
CONT_ASSIGN134411100.00
CONT_ASSIGN136011100.00
CONT_ASSIGN137611100.00
CONT_ASSIGN139211100.00
CONT_ASSIGN139811100.00
CONT_ASSIGN141211100.00
CONT_ASSIGN177311100.00
CONT_ASSIGN180111100.00
CONT_ASSIGN182911100.00
CONT_ASSIGN185711100.00
CONT_ASSIGN188511100.00
CONT_ASSIGN191311100.00
CONT_ASSIGN195411100.00
CONT_ASSIGN198211100.00
CONT_ASSIGN201011100.00
CONT_ASSIGN203811100.00
CONT_ASSIGN207911100.00
CONT_ASSIGN210711100.00
CONT_ASSIGN214811100.00
CONT_ASSIGN217611100.00
CONT_ASSIGN220411100.00
CONT_ASSIGN290111100.00
CONT_ASSIGN301911100.00
CONT_ASSIGN303411100.00
CONT_ASSIGN305011100.00
ALWAYS31843232100.00
CONT_ASSIGN321811100.00
ALWAYS322211100.00
CONT_ASSIGN325711100.00
CONT_ASSIGN325911100.00
CONT_ASSIGN326111100.00
CONT_ASSIGN326311100.00
CONT_ASSIGN326511100.00
CONT_ASSIGN326711100.00
CONT_ASSIGN326911100.00
CONT_ASSIGN327111100.00
CONT_ASSIGN327311100.00
CONT_ASSIGN327411100.00
CONT_ASSIGN327611100.00
CONT_ASSIGN327811100.00
CONT_ASSIGN328011100.00
CONT_ASSIGN328211100.00
CONT_ASSIGN328411100.00
CONT_ASSIGN328611100.00
CONT_ASSIGN328811100.00
CONT_ASSIGN329011100.00
CONT_ASSIGN329211100.00
CONT_ASSIGN329411100.00
CONT_ASSIGN329611100.00
CONT_ASSIGN329811100.00
CONT_ASSIGN330011100.00
CONT_ASSIGN330211100.00
CONT_ASSIGN330411100.00
CONT_ASSIGN330511100.00
CONT_ASSIGN330711100.00
CONT_ASSIGN330911100.00
CONT_ASSIGN331111100.00
CONT_ASSIGN331311100.00
CONT_ASSIGN331511100.00
CONT_ASSIGN331711100.00
CONT_ASSIGN331911100.00
CONT_ASSIGN332111100.00
CONT_ASSIGN332311100.00
CONT_ASSIGN332511100.00
CONT_ASSIGN332711100.00
CONT_ASSIGN332911100.00
CONT_ASSIGN333111100.00
CONT_ASSIGN333311100.00
CONT_ASSIGN333511100.00
CONT_ASSIGN333611100.00
CONT_ASSIGN333811100.00
CONT_ASSIGN333911100.00
CONT_ASSIGN334111100.00
CONT_ASSIGN334311100.00
CONT_ASSIGN334511100.00
CONT_ASSIGN334711100.00
CONT_ASSIGN334911100.00
CONT_ASSIGN335011100.00
CONT_ASSIGN335111100.00
CONT_ASSIGN335211100.00
CONT_ASSIGN335411100.00
CONT_ASSIGN335611100.00
CONT_ASSIGN335811100.00
CONT_ASSIGN336011100.00
CONT_ASSIGN336211100.00
CONT_ASSIGN336411100.00
CONT_ASSIGN336511100.00
CONT_ASSIGN336711100.00
CONT_ASSIGN336911100.00
CONT_ASSIGN337111100.00
CONT_ASSIGN337311100.00
CONT_ASSIGN337411100.00
CONT_ASSIGN337611100.00
CONT_ASSIGN337811100.00
CONT_ASSIGN337911100.00
CONT_ASSIGN338111100.00
CONT_ASSIGN338311100.00
CONT_ASSIGN338511100.00
CONT_ASSIGN338611100.00
CONT_ASSIGN338711100.00
CONT_ASSIGN338811100.00
CONT_ASSIGN339011100.00
CONT_ASSIGN339211100.00
CONT_ASSIGN339411100.00
CONT_ASSIGN339511100.00
CONT_ASSIGN339611100.00
CONT_ASSIGN339811100.00
CONT_ASSIGN340011100.00
CONT_ASSIGN340111100.00
CONT_ASSIGN340311100.00
CONT_ASSIGN340511100.00
CONT_ASSIGN340611100.00
CONT_ASSIGN340811100.00
CONT_ASSIGN341011100.00
CONT_ASSIGN341111100.00
CONT_ASSIGN341311100.00
CONT_ASSIGN341511100.00
CONT_ASSIGN341611100.00
CONT_ASSIGN341811100.00
CONT_ASSIGN342011100.00
CONT_ASSIGN342111100.00
CONT_ASSIGN342311100.00
CONT_ASSIGN342511100.00
CONT_ASSIGN342611100.00
CONT_ASSIGN342811100.00
CONT_ASSIGN343011100.00
CONT_ASSIGN343211100.00
CONT_ASSIGN343411100.00
CONT_ASSIGN343511100.00
CONT_ASSIGN343611100.00
CONT_ASSIGN343811100.00
CONT_ASSIGN343911100.00
CONT_ASSIGN344111100.00
CONT_ASSIGN344211100.00
CONT_ASSIGN344411100.00
CONT_ASSIGN344611100.00
CONT_ASSIGN344711100.00
CONT_ASSIGN345011100.00
CONT_ASSIGN345111100.00
CONT_ASSIGN345311100.00
CONT_ASSIGN345511100.00
CONT_ASSIGN345611100.00
CONT_ASSIGN345711100.00
CONT_ASSIGN345911100.00
CONT_ASSIGN346111100.00
CONT_ASSIGN346211100.00
CONT_ASSIGN346411100.00
CONT_ASSIGN346611100.00
ALWAYS34703232100.00
ALWAYS3506119119100.00
CONT_ASSIGN372900
CONT_ASSIGN373711100.00
CONT_ASSIGN373811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
1153 1 1
1168 1 1
1184 1 1
1200 1 1
1216 1 1
1232 1 1
1248 1 1
1264 1 1
1280 1 1
1296 1 1
1312 1 1
1328 1 1
1344 1 1
1360 1 1
1376 1 1
1392 1 1
1398 1 1
1412 1 1
1773 1 1
1801 1 1
1829 1 1
1857 1 1
1885 1 1
1913 1 1
1954 1 1
1982 1 1
2010 1 1
2038 1 1
2079 1 1
2107 1 1
2148 1 1
2176 1 1
2204 1 1
2901 1 1
3019 1 1
3034 1 1
3050 1 1
3184 1 1
3185 1 1
3186 1 1
3187 1 1
3188 1 1
3189 1 1
3190 1 1
3191 1 1
3192 1 1
3193 1 1
3194 1 1
3195 1 1
3196 1 1
3197 1 1
3198 1 1
3199 1 1
3200 1 1
3201 1 1
3202 1 1
3203 1 1
3204 1 1
3205 1 1
3206 1 1
3207 1 1
3208 1 1
3209 1 1
3210 1 1
3211 1 1
3212 1 1
3213 1 1
3214 1 1
3215 1 1
3218 1 1
3222 1 1
3257 1 1
3259 1 1
3261 1 1
3263 1 1
3265 1 1
3267 1 1
3269 1 1
3271 1 1
3273 1 1
3274 1 1
3276 1 1
3278 1 1
3280 1 1
3282 1 1
3284 1 1
3286 1 1
3288 1 1
3290 1 1
3292 1 1
3294 1 1
3296 1 1
3298 1 1
3300 1 1
3302 1 1
3304 1 1
3305 1 1
3307 1 1
3309 1 1
3311 1 1
3313 1 1
3315 1 1
3317 1 1
3319 1 1
3321 1 1
3323 1 1
3325 1 1
3327 1 1
3329 1 1
3331 1 1
3333 1 1
3335 1 1
3336 1 1
3338 1 1
3339 1 1
3341 1 1
3343 1 1
3345 1 1
3347 1 1
3349 1 1
3350 1 1
3351 1 1
3352 1 1
3354 1 1
3356 1 1
3358 1 1
3360 1 1
3362 1 1
3364 1 1
3365 1 1
3367 1 1
3369 1 1
3371 1 1
3373 1 1
3374 1 1
3376 1 1
3378 1 1
3379 1 1
3381 1 1
3383 1 1
3385 1 1
3386 1 1
3387 1 1
3388 1 1
3390 1 1
3392 1 1
3394 1 1
3395 1 1
3396 1 1
3398 1 1
3400 1 1
3401 1 1
3403 1 1
3405 1 1
3406 1 1
3408 1 1
3410 1 1
3411 1 1
3413 1 1
3415 1 1
3416 1 1
3418 1 1
3420 1 1
3421 1 1
3423 1 1
3425 1 1
3426 1 1
3428 1 1
3430 1 1
3432 1 1
3434 1 1
3435 1 1
3436 1 1
3438 1 1
3439 1 1
3441 1 1
3442 1 1
3444 1 1
3446 1 1
3447 1 1
3450 1 1
3451 1 1
3453 1 1
3455 1 1
3456 1 1
3457 1 1
3459 1 1
3461 1 1
3462 1 1
3464 1 1
3466 1 1
3470 1 1
3471 1 1
3472 1 1
3473 1 1
3474 1 1
3475 1 1
3476 1 1
3477 1 1
3478 1 1
3479 1 1
3480 1 1
3481 1 1
3482 1 1
3483 1 1
3484 1 1
3485 1 1
3486 1 1
3487 1 1
3488 1 1
3489 1 1
3490 1 1
3491 1 1
3492 1 1
3493 1 1
3494 1 1
3495 1 1
3496 1 1
3497 1 1
3498 1 1
3499 1 1
3500 1 1
3501 1 1
3506 1 1
3507 1 1
3509 1 1
3510 1 1
3511 1 1
3512 1 1
3513 1 1
3514 1 1
3515 1 1
3516 1 1
3517 1 1
3518 1 1
3519 1 1
3520 1 1
3521 1 1
3522 1 1
3523 1 1
3527 1 1
3528 1 1
3529 1 1
3530 1 1
3531 1 1
3532 1 1
3533 1 1
3534 1 1
3535 1 1
3536 1 1
3537 1 1
3538 1 1
3539 1 1
3540 1 1
3541 1 1
3545 1 1
3546 1 1
3547 1 1
3548 1 1
3549 1 1
3550 1 1
3551 1 1
3552 1 1
3553 1 1
3554 1 1
3555 1 1
3556 1 1
3557 1 1
3558 1 1
3559 1 1
3563 1 1
3567 1 1
3568 1 1
3569 1 1
3570 1 1
3571 1 1
3575 1 1
3576 1 1
3577 1 1
3578 1 1
3579 1 1
3580 1 1
3581 1 1
3582 1 1
3583 1 1
3584 1 1
3585 1 1
3589 1 1
3593 1 1
3594 1 1
3595 1 1
3596 1 1
3597 1 1
3598 1 1
3602 1 1
3603 1 1
3604 1 1
3605 1 1
3609 1 1
3610 1 1
3614 1 1
3615 1 1
3616 1 1
3620 1 1
3621 1 1
3625 1 1
3626 1 1
3630 1 1
3631 1 1
3632 1 1
3636 1 1
3637 1 1
3641 1 1
3642 1 1
3646 1 1
3647 1 1
3651 1 1
3652 1 1
3656 1 1
3657 1 1
3661 1 1
3662 1 1
3666 1 1
3667 1 1
3671 1 1
3672 1 1
3673 1 1
3674 1 1
3678 1 1
3679 1 1
3683 1 1
3687 1 1
3691 1 1
3692 1 1
3696 1 1
3700 1 1
3701 1 1
3705 1 1
3709 1 1
3710 1 1
3714 1 1
3715 1 1
3729 unreachable
3737 1 1
3738 1 1


Cond Coverage for Module : i2c_reg_top
TotalCoveredPercent
Conditions33733599.41
Logical33733599.41
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT118,T126,T127
11CoveredT1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT61,T120,T121
10CoveredT80,T128,T129

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT61,T120,T121
010CoveredT80,T128,T129
100CoveredT61,T120,T121

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT80,T128,T129
010CoveredT118,T119,T125
100CoveredT118,T126,T127

 LINE       3185
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3186
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3187
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3188
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3189
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3190
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3191
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3192
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3193
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3194
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3195
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3196
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3197
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3198
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       3199
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3200
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3201
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3202
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3203
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3204
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3205
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3206
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3207
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3208
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3209
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3210
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_TIMEOUT_CTRL_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3211
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_NACK_COUNT_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3212
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ACK_CTRL_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3213
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQ_FIFO_NEXT_DATA_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3214
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3215
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CONTROLLER_EVENTS_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3218
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3218
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       3222
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT118,T80,T119

 LINE       3222
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
31 (addr_hit[30] & ((|(4'...CoveredT3,T4,T5
30 (addr_hit[29] & ((|(4'...CoveredT3,T4,T5
29 (addr_hit[28] & ((|(4'...CoveredT3,T4,T5
28 (addr_hit[27] & ((|(4'...CoveredT3,T4,T5
27 (addr_hit[26] & ((|(4'...CoveredT3,T4,T5
26 (addr_hit[25] & ((|(4'...CoveredT3,T4,T5
25 (addr_hit[24] & ((|(4'...CoveredT3,T4,T5
24 (addr_hit[23] & ((|(4'...CoveredT3,T4,T5
23 (addr_hit[22] & ((|(4'...CoveredT3,T4,T5
22 (addr_hit[21] & ((|(4'...CoveredT3,T4,T5
21 (addr_hit[20] & ((|(4'...CoveredT3,T4,T5
20 (addr_hit[19] & ((|(4'...CoveredT3,T4,T5
19 (addr_hit[18] & ((|(4'...CoveredT3,T4,T5
18 (addr_hit[17] & ((|(4'...CoveredT3,T4,T5
17 (addr_hit[16] & ((|(4'...CoveredT3,T4,T5
16 (addr_hit[15] & ((|(4'...CoveredT3,T4,T5
15 (addr_hit[14] & ((|(4'...CoveredT3,T4,T5
14 (addr_hit[13] & ((|(4'...CoveredT1,T3,T4
13 (addr_hit[12] & ((|(4'...CoveredT3,T4,T5
12 (addr_hit[11] & ((|(4'...CoveredT3,T4,T5
11 (addr_hit[10] & ((|(4'...CoveredT3,T4,T5
10 (addr_hit[9] & ((|(4'b...CoveredT3,T4,T5
9 (addr_hit[8] & ((|(4'b...CoveredT3,T4,T5
8 (addr_hit[7] & ((|(4'b...CoveredT3,T4,T5
7 (addr_hit[6] & ((|(4'b...CoveredT2,T3,T4
6 (addr_hit[5] & ((|(4'b...CoveredT2,T3,T4
5 (addr_hit[4] & ((|(4'b...CoveredT3,T4,T5
4 (addr_hit[3] & ((|(4'b...CoveredT3,T4,T5
3 (addr_hit[2] & ((|(4'b...CoveredT3,T4,T5
2 (addr_hit[1] & ((|(4'b...CoveredT3,T4,T5
1 (addr_hit[0] & ((|(4'b...CoveredT2,T3,T4

 LINE       3222
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       3222
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       3222
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       3222
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       3222
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT3,T4,T5

 LINE       3222
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       3257
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT118,T126,T127
111CoveredT1,T2,T3

 LINE       3274
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT118,T80,T130
111CoveredT1,T2,T3

 LINE       3305
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT118,T131,T132
111CoveredT42,T75,T83

 LINE       3336
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT126,T131,T133
111CoveredT115,T116,T117

 LINE       3339
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT127,T128,T131
111CoveredT1,T2,T3

 LINE       3350
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT80
111CoveredT2,T3,T4

 LINE       3351
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT134,T135
111CoveredT2,T4,T7

 LINE       3352
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT128,T133,T136
111CoveredT2,T4,T6

 LINE       3365
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT119,T126,T131
111CoveredT1,T2,T3

 LINE       3374
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT118,T126,T127
111CoveredT2,T3,T4

 LINE       3379
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT118,T126,T128
111CoveredT2,T3,T4

 LINE       3386
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110Not Covered
111CoveredT43,T41,T73

 LINE       3387
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT137
111CoveredT3,T5,T10

 LINE       3388
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T4
110CoveredT126,T127,T133
111CoveredT1,T8,T39

 LINE       3395
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT138,T139,T140
111Not Covered

 LINE       3396
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT125,T127,T131
111CoveredT2,T3,T4

 LINE       3401
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT118,T126,T131
111CoveredT2,T3,T4

 LINE       3406
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT118,T125,T131
111CoveredT2,T3,T4

 LINE       3411
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT118,T127,T131
111CoveredT2,T3,T4

 LINE       3416
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT126,T127,T132
111CoveredT2,T3,T4

 LINE       3421
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT126,T133,T132
111CoveredT2,T3,T4

 LINE       3426
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT126,T127,T131
111CoveredT3,T5,T10

 LINE       3435
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT141,T140,T135
111CoveredT3,T5,T10

 LINE       3436
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT126,T127,T131
111CoveredT3,T10,T19

 LINE       3439
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT126,T127,T131
111CoveredT3,T5,T10

 LINE       3442
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT126,T127,T131
111CoveredT80,T81,T82

 LINE       3447
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT129,T142,T143
111CoveredT80,T81,T82

 LINE       3450
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT144
111CoveredT80,T81,T82

 LINE       3451
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT80,T126,T131
111CoveredT5,T14,T15

 LINE       3456
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT145,T137,T143
111CoveredT80,T81,T82

 LINE       3457
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT125,T126,T127
111CoveredT67,T69,T70

 LINE       3462
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT126,T131,T133
111CoveredT1,T2,T3

Branch Coverage for Module : i2c_reg_top
Line No.TotalCoveredPercent
Branches 37 37 100.00
TERNARY 3218 2 2 100.00
IF 68 3 3 100.00
CASE 3507 32 32 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 3218 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T61,T120,T121
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 3507 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : i2c_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 402560315 54544758 0 0
reAfterRv 402560315 54544590 0 0
rePulse 402560315 53623078 0 0
wePulse 402560315 921512 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 402560315 54544758 0 0
T1 2464 27 0 0
T2 36212 17049 0 0
T3 62825 727 0 0
T4 157439 22375 0 0
T5 827856 844 0 0
T6 31017 14045 0 0
T7 143322 20389 0 0
T8 1762 40 0 0
T9 4915 211 0 0
T10 61698 838 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 402560315 54544590 0 0
T1 2464 27 0 0
T2 36212 17049 0 0
T3 62825 727 0 0
T4 157439 22375 0 0
T5 827856 844 0 0
T6 31017 14045 0 0
T7 143322 20389 0 0
T8 1762 40 0 0
T9 4915 211 0 0
T10 61698 838 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 402560315 53623078 0 0
T1 2464 13 0 0
T2 36212 16684 0 0
T3 62825 526 0 0
T4 157439 21527 0 0
T5 827856 764 0 0
T6 31017 13754 0 0
T7 143322 20261 0 0
T8 1762 20 0 0
T9 4915 119 0 0
T10 61698 627 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 402560315 921512 0 0
T1 2464 14 0 0
T2 36212 365 0 0
T3 62825 201 0 0
T4 157439 848 0 0
T5 827856 80 0 0
T6 31017 291 0 0
T7 143322 128 0 0
T8 1762 20 0 0
T9 4915 92 0 0
T10 61698 211 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%