Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.72 100.00 100.00 94.87 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.72 100.00 100.00 94.87 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.72 100.00 100.00 94.87 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.94 97.19 91.83 97.66 83.74 94.53 98.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
i2c_core 90.71 96.14 86.79 83.74 92.17 94.74
i2c_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_reg 98.84 98.58 98.18 100.00 97.42 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
129 1 1
130 1 1


Cond Coverage for Module : i2c
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT115,T116,T117
10CoveredT1,T2,T3
11CoveredT115,T116,T117

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 49 45 91.84
Total Bits 390 370 94.87
Total Bits 0->1 195 185 94.87
Total Bits 1->0 195 185 94.87

Ports 49 45 91.84
Port Bits 390 370 94.87
Port Bits 0->1 195 185 94.87
Port Bits 1->0 195 185 94.87

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T9,T59,T61 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T118,T80,T119 Yes T118,T80,T119 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T61,T115,T116 Yes T61,T115,T116 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T61,T115,T116 Yes T61,T115,T116 OUTPUT
cio_scl_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_sda_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fmt_threshold_o Yes Yes T2,T6,T7 Yes T2,T3,T4 OUTPUT
intr_rx_threshold_o Yes Yes T7,T43,T40 Yes T7,T43,T40 OUTPUT
intr_acq_threshold_o Yes Yes T58,T23,T37 Yes T58,T23,T37 OUTPUT
intr_rx_overflow_o Yes Yes T7,T40,T42 Yes T7,T40,T42 OUTPUT
intr_controller_halt_o Yes Yes T67,T42,T69 Yes T67,T42,T69 OUTPUT
intr_scl_interference_o Yes Yes T42,T75,T83 Yes T42,T75,T83 OUTPUT
intr_sda_interference_o Yes Yes T2,T4,T6 Yes T1,T2,T4 OUTPUT
intr_stretch_timeout_o Yes Yes T2,T4,T6 Yes T2,T4,T6 OUTPUT
intr_sda_unstable_o Yes Yes T2,T4,T6 Yes T2,T4,T6 OUTPUT
intr_cmd_complete_o Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
intr_tx_stretch_o Yes Yes T3,T10,T19 Yes T3,T10,T19 OUTPUT
intr_tx_threshold_o Yes Yes T3,T9,T10 Yes T2,T3,T4 OUTPUT
intr_acq_stretch_o Yes Yes T5,T14,T23 Yes T5,T14,T23 OUTPUT
intr_unexp_stop_o Yes Yes T42,T75,T20 Yes T42,T75,T20 OUTPUT
intr_host_timeout_o Yes Yes T42,T75,T11 Yes T42,T75,T11 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : i2c
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 401286863 401107816 0 0
CioSclEnKnownO_A 401286863 401107816 0 0
CioSclKnownO_A 401286863 401107816 0 0
CioSdaEnKnownO_A 401286863 401107816 0 0
CioSdaKnownO_A 401286863 401107816 0 0
FpvSecCmRegWeOnehotCheck_A 401286863 100 0 0
IntrAcqStretchKnownO_A 401286863 401107816 0 0
IntrAcqWtmkKnownO_A 401286863 401107816 0 0
IntrCommandCompleteKnownO_A 401286863 401107816 0 0
IntrControllerHaltKnownO_A 401286863 401107816 0 0
IntrFmtWtmkKnownO_A 401286863 401107816 0 0
IntrHostTimeoutKnownO_A 401286863 401107816 0 0
IntrRxOflwKnownO_A 401286863 401107816 0 0
IntrRxWtmkKnownO_A 401286863 401107816 0 0
IntrSclInterfKnownO_A 401286863 401107816 0 0
IntrSdaInterfKnownO_A 401286863 401107816 0 0
IntrSdaUnstableKnownO_A 401286863 401107816 0 0
IntrStretchTimeoutKnownO_A 401286863 401107816 0 0
IntrTxStretchKnownO_A 401286863 401107816 0 0
IntrTxWtmkKnownO_A 401286863 401107816 0 0
IntrUnexpStopKnownO_A 401286863 401107816 0 0
TlAReadyKnownO_A 401286863 401107816 0 0
TlDValidKnownO_A 401286863 401107816 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

CioSclEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

CioSclKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

CioSdaEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

CioSdaKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 100 0 0
T15 100770 0 0 0
T24 612589 0 0 0
T25 466627 0 0 0
T32 61075 0 0 0
T40 158106 0 0 0
T41 8296 0 0 0
T61 6264 20 0 0
T67 27739 0 0 0
T73 7166 0 0 0
T120 0 20 0 0
T121 0 20 0 0
T122 0 20 0 0
T123 0 20 0 0
T124 1707 0 0 0

IntrAcqStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrAcqWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrCommandCompleteKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrControllerHaltKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrFmtWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrHostTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrRxOflwKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrRxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrSclInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrSdaInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrSdaUnstableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrStretchTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrTxStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrTxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

IntrUnexpStopKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401286863 401107816 0 0
T1 2464 2364 0 0
T2 36212 36135 0 0
T3 62825 62735 0 0
T4 157439 157378 0 0
T5 827856 827760 0 0
T6 31017 30936 0 0
T7 143322 143243 0 0
T8 1762 1690 0 0
T9 4915 4410 0 0
T10 61698 61613 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%