Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	402560315	7684	0	0
ctrl_rd_A	402560315	1705	0	0
host_fifo_config_rd_A	402560315	5009	0	0
host_nack_handler_timeout_rd_A	402560315	1328	0	0
host_timeout_ctrl_rd_A	402560315	1220	0	0
intr_enable_rd_A	402560315	3224	0	0
ovrd_rd_A	402560315	2144	0	0
target_fifo_config_rd_A	402560315	1550	0	0
target_id_rd_A	402560315	1517	0	0
target_timeout_ctrl_rd_A	402560315	1361	0	0
timeout_ctrl_rd_A	402560315	1347	0	0
timing0_rd_A	402560315	1230	0	0
timing1_rd_A	402560315	1375	0	0
timing2_rd_A	402560315	1304	0	0
timing3_rd_A	402560315	1415	0	0
timing4_rd_A	402560315	1414	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	7684	0	0
T80	15048	1	0	0
T118	2977	334	0	0
T119	3794	6	0	0
T125	2228	8	0	0
T126	13864	579	0	0
T127	13268	563	0	0
T129	8002	1	0	0
T130	1552	2	0	0
T131	10605	463	0	0
T147	2128	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1705	0	0
T80	15048	175	0	0
T119	3794	41	0	0
T125	2228	22	0	0
T126	13864	33	0	0
T127	13268	17	0	0
T129	8002	122	0	0
T131	10605	12	0	0
T136	10849	14	0	0
T138	13955	150	0	0
T147	2128	10	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	5009	0	0
T14	992609	0	0	0
T15	100770	0	0	0
T23	534114	0	0	0
T24	612589	0	0	0
T37	963897	0	0	0
T39	2515	0	0	0
T43	253139	84	0	0
T59	5990	0	0	0
T60	114023	0	0	0
T61	6264	0	0	0
T75	0	157	0	0
T168	0	227	0	0
T169	0	156	0	0
T170	0	187	0	0
T171	0	55	0	0
T172	0	145	0	0
T173	0	211	0	0
T174	0	104	0	0
T175	0	178	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1328	0	0
T80	15048	110	0	0
T119	3794	9	0	0
T125	2228	8	0	0
T126	13864	8	0	0
T127	13268	36	0	0
T129	8002	48	0	0
T131	10605	7	0	0
T138	13955	65	0	0
T147	2128	7	0	0
T153	1427	2	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1220	0	0
T80	15048	84	0	0
T119	3794	14	0	0
T125	2228	9	0	0
T126	13864	37	0	0
T127	13268	12	0	0
T129	8002	25	0	0
T131	10605	17	0	0
T136	10849	20	0	0
T138	13955	35	0	0
T147	2128	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	3224	0	0
T20	129899	0	0	0
T29	34899	0	0	0
T55	482043	0	0	0
T75	124503	48	0	0
T83	0	10	0	0
T89	15747	0	0	0
T114	179159	0	0	0
T115	1350	0	0	0
T169	0	18	0	0
T175	0	15	0	0
T176	0	33	0	0
T177	0	30	0	0
T178	0	35	0	0
T179	0	13	0	0
T180	0	8	0	0
T181	0	26	0	0
T182	551987	0	0	0
T183	9363	0	0	0
T184	86933	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	2144	0	0
T8	1762	64	0	0
T9	4915	0	0	0
T10	61698	0	0	0
T14	992609	0	0	0
T19	66221	0	0	0
T35	211572	0	0	0
T36	249679	0	0	0
T39	0	57	0	0
T43	253139	0	0	0
T58	534834	0	0	0
T59	5990	0	0	0
T185	0	37	0	0
T186	0	42	0	0
T187	0	15	0	0
T188	0	73	0	0
T189	0	25	0	0
T190	0	73	0	0
T191	0	30	0	0
T192	0	46	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1550	0	0
T80	15048	121	0	0
T119	3794	33	0	0
T125	2228	6	0	0
T126	13864	53	0	0
T127	13268	3	0	0
T129	8002	68	0	0
T131	10605	19	0	0
T136	10849	25	0	0
T138	13955	113	0	0
T147	2128	10	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1517	0	0
T80	15048	194	0	0
T119	3794	23	0	0
T125	2228	8	0	0
T126	13864	36	0	0
T129	8002	108	0	0
T131	10605	16	0	0
T136	10849	16	0	0
T138	13955	112	0	0
T147	2128	3	0	0
T193	8202	7	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1361	0	0
T80	15048	107	0	0
T119	3794	26	0	0
T125	2228	3	0	0
T126	13864	9	0	0
T127	13268	16	0	0
T129	8002	64	0	0
T131	10605	12	0	0
T136	10849	64	0	0
T138	13955	61	0	0
T193	8202	9	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1347	0	0
T80	15048	129	0	0
T119	3794	43	0	0
T125	2228	6	0	0
T126	13864	42	0	0
T127	13268	5	0	0
T129	8002	62	0	0
T136	10849	40	0	0
T138	13955	44	0	0
T145	7768	31	0	0
T193	8202	11	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1230	0	0
T80	15048	103	0	0
T119	3794	37	0	0
T125	2228	9	0	0
T126	13864	26	0	0
T127	13268	7	0	0
T129	8002	54	0	0
T131	10605	10	0	0
T136	10849	8	0	0
T138	13955	61	0	0
T147	2128	5	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1375	0	0
T80	15048	126	0	0
T119	3794	35	0	0
T125	2228	12	0	0
T126	13864	55	0	0
T127	13268	1	0	0
T129	8002	46	0	0
T131	10605	7	0	0
T138	13955	54	0	0
T147	2128	11	0	0
T153	1427	8	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1304	0	0
T80	15048	107	0	0
T119	3794	12	0	0
T125	2228	3	0	0
T126	13864	23	0	0
T127	13268	10	0	0
T129	8002	61	0	0
T131	10605	6	0	0
T138	13955	68	0	0
T147	2128	9	0	0
T153	1427	4	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1415	0	0
T80	15048	136	0	0
T119	3794	18	0	0
T125	2228	5	0	0
T126	13864	28	0	0
T127	13268	13	0	0
T129	8002	77	0	0
T131	10605	28	0	0
T138	13955	39	0	0
T147	2128	5	0	0
T153	1427	5	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402560315	1414	0	0
T80	15048	118	0	0
T119	3794	11	0	0
T125	2228	18	0	0
T127	13268	2	0	0
T129	8002	50	0	0
T131	10605	16	0	0
T136	10849	22	0	0
T138	13955	71	0	0
T145	7768	45	0	0
T193	8202	7	0	0