Unified Coverage Report :: Module :: i2c_core

Module : i2c_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.64	97.25	73.63			91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core	90.64	97.25	73.63			91.67	100.00

---

Module Instance : tb.dut.i2c_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.64	97.25	73.63			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.83	96.19	87.17		83.74	92.31	94.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_acq_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_acq_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_cmd_complete	100.00	100.00	100.00			100.00	100.00
intr_hw_controller_halt	100.00	100.00	100.00			100.00	100.00
intr_hw_fmt_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_host_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_scl_interference	100.00	100.00	100.00			100.00	100.00
intr_hw_sda_interference	100.00	100.00	100.00			100.00	100.00
intr_hw_sda_unstable	100.00	100.00	100.00			100.00	100.00
intr_hw_stretch_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_stretch	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_threshold	100.00	100.00	100.00			100.00	100.00
intr_hw_unexp_stop	100.00	100.00	100.00			100.00	100.00
u_fifos	94.64	99.86	86.59			98.65	93.48
u_i2c_controller_fsm	94.22	95.06	92.17		90.91	92.94	100.00
u_i2c_sync_scl	100.00	100.00				100.00
u_i2c_sync_sda	100.00	100.00				100.00
u_i2c_target_fsm	85.45	88.43	79.05		81.11	78.65	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
TOTAL		109	106	97.25
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
ALWAYS	232	5	5	100.00
ALWAYS	244	5	5	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	332	1	0	0.00
CONT_ASSIGN	333	1	0	0.00
CONT_ASSIGN	334	1	0	0.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
207	1	1
208	1	1
210	1	1
212	1	1
213	1	1
215	1	1
216	1	1
217	1	1
219	1	1
223	1	1
225	1	1
226	1	1
227	1	1
228	1	1
232	1	1
233	1	1
234	1	1
237	1	1
238	1	1
244	1	1
245	1	1
246	1	1
248	1	1
249	1	1
253	1	1
254	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
273	1	1
274	1	1
275	1	1
276	1	1
278	1	1
280	1	1
281	1	1
282	1	1
285	1	1
287	1	1
289	1	1
291	1	1
293	1	1
294	1	1
299	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
326	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	0	1
333	0	1
334	0	1
335	1	1
336	1	1
337	1	1
381	1	1
386	1	1
388	1	1
391	1	1
392	1	1
397	1	1
742	1	1
744	1	1
745	1	1

---

Cond Coverage for Module : i2c_core

	Total	Covered	Percent
Conditions	91	67	73.63
Logical	91	67	73.63
Non-Logical	0	0
Event	0	0

 LINE       207
 EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       212
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T35,T36

 LINE       213
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T35,T36

 LINE       219
 EXPRESSION (event_controller_cmd_complete | event_target_cmd_complete)
             --------------1--------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T10

 LINE       223
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T5,T6
1	1	Not Covered

 LINE       237
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (reg2hw.target_ack_ctrl.nack.qe & reg2hw.target_ack_ctrl.nack.q)
             ---------------1--------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T9
1	1	Not Covered

 LINE       273
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       278
 EXPRESSION ((reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe) || (reg2hw.target_fifo_config.txrst_on_cond.q & target_sr_p_cond))
             ---------------------------1--------------------------    -------------------------------2------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       278
 SUB-EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T39
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       278
 SUB-EXPRESSION (reg2hw.target_fifo_config.txrst_on_cond.q & target_sr_p_cond)
                 --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       280
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T40
1	1	Covered	T39,T41,T42

 LINE       294
 EXPRESSION (acq_fifo_full || target_ack_ctrl_stretching)
             ------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T20,T21,T22

 LINE       299
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Not Covered
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Not Covered
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Not Covered
1	1	1	1	1	0	Not Covered
1	1	1	1	1	1	Covered	T1,T2,T10

 LINE       312
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       313
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       314
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       315
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       316
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       317
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       388
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       388
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       391
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       391
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       392
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       397
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T5,T6

 LINE       397
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T5,T6

 LINE       397
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       397
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T43,T37
1	0	Covered	T1,T2,T3

 LINE       397
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T6

---

Branch Coverage for Module : i2c_core

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	212	2	2	100.00
TERNARY	213	2	2	100.00
TERNARY	312	2	2	100.00
TERNARY	313	2	2	100.00
TERNARY	314	2	2	100.00
TERNARY	315	2	2	100.00
TERNARY	316	2	2	100.00
TERNARY	317	2	2	100.00
TERNARY	391	2	1	50.00
TERNARY	392	2	1	50.00
IF	232	2	2	100.00
IF	244	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	213	(override) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	312	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	313	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	314	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	317	(fmt_fifo_rvalid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	(target_loopback) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	232	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqFifoDepthValid_A	1311	1311	0	0
FifoDepthValid_A	1311	1311	0	0
SclInputGlitch_A	389780304	9454269	0	0

AcqFifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1311	1311	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

FifoDepthValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1311	1311	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SclInputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389780304	9454269	0	0
T1	15099	730	0	0
T2	343188	17580	0	0
T3	89998	4514	0	0
T4	936	0	0	0
T5	71872	3703	0	0
T6	260947	12461	0	0
T7	64343	2665	0	0
T8	176295	7507	0	0
T9	49009	2530	0	0
T10	320855	17580	0	0
T11	0	6180	0	0