Unified Coverage Report :: Module :: i2c_controller_fsm

Module : i2c_controller_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22	95.06	92.17		90.91	92.94	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_controller_fsm	94.22	95.06	92.17		90.91	92.94	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_controller_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22	95.06	92.17		90.91	92.94	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22	95.06	92.17		90.91	92.94	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.64	97.25	73.63			91.67	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_controller_fsm

	Line No.	Total	Covered	Percent
TOTAL		405	385	95.06
ALWAYS	118	16	16	100.00
ALWAYS	144	3	3	100.00
ALWAYS	157	5	5	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	184	6	6	100.00
ALWAYS	200	9	8	88.89
CONT_ASSIGN	215	1	1	100.00
ALWAYS	219	7	7	100.00
ALWAYS	232	6	6	100.00
ALWAYS	243	5	5	100.00
ALWAYS	250	7	7	100.00
ALWAYS	263	5	5	100.00
ALWAYS	277	8	8	100.00
ALWAYS	289	8	7	87.50
ALWAYS	301	3	3	100.00
CONT_ASSIGN	343	1	1	100.00
ALWAYS	348	6	6	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
ALWAYS	376	119	116	97.48
ALWAYS	579	181	166	91.71
ALWAYS	910	3	3	100.00
CONT_ASSIGN	917	1	1	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	921	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
119	1	1
120	1	1
121	1	1
122	1	1
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
134	1	1
139	1	1
			MISSING_ELSE
144	1	1
145	1	1
147	1	1
157	1	1
158	1	1
159	1	1
161	1	1
163	1	1
180	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
			MISSING_ELSE
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	0	1
			MISSING_ELSE
210	1	1
211	1	1
215	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
226	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
243	2	2
244	2	2
245	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
255	1	1
257	1	1
263	1	1
264	1	1
265	1	1
267	1	1
268	1	1
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
			MISSING_ELSE
289	1	1
290	1	1
291	1	1
292	0	1
293	1	1
294	1	1
295	1	1
296	1	1
			MISSING_ELSE
301	1	1
302	1	1
304	1	1
343	1	1
348	1	1
349	1	1
350	1	1
354	1	1
355	1	1
356	1	1
			MISSING_ELSE
366	1	1
371	1	1
376	1	1
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
386	1	1
387	1	1
392	1	1
393	1	1
394	1	1
395	1	1
397	1	1
398	1	1
408	1	1
409	1	1
410	1	1
411	2	2
			MISSING_ELSE
415	1	1
416	1	1
417	1	1
421	1	1
422	1	1
423	1	1
426	1	1
427	1	1
428	1	1
430	1	1
432	1	1
436	1	1
437	1	1
438	1	1
439	1	1
440	1	2
			MISSING_ELSE
441	2	2
			MISSING_ELSE
445	1	1
446	1	1
447	1	1
451	1	1
452	1	1
453	1	1
457	1	1
458	1	1
459	1	1
460	2	2
			MISSING_ELSE
461	1	1
462	1	2
			MISSING_ELSE
463	2	2
			MISSING_ELSE
467	1	1
468	1	1
469	1	1
473	1	1
474	1	1
475	1	1
479	1	1
480	1	1
481	1	1
482	2	2
			MISSING_ELSE
483	2	2
			MISSING_ELSE
487	1	1
488	1	1
489	1	1
490	1	1
491	1	1
			MISSING_ELSE
496	1	1
497	1	1
501	2	2
502	2	2
503	1	1
507	1	1
508	2	2
509	2	2
510	1	1
511	1	1
512	1	1
513	1	2
			MISSING_ELSE
514	2	2
			MISSING_ELSE
518	1	1
519	2	2
520	2	2
521	1	1
522	1	1
526	1	1
527	1	1
528	1	1
532	1	1
533	1	1
534	1	1
538	1	1
539	1	1
540	1	1
541	1	1
545	1	1
551	1	1
555	1	1
556	2	2
557	1	1
558	1	1
579	1	1
580	1	1
581	1	1
582	1	1
583	1	1
584	1	1
585	1	1
586	1	1
587	1	1
588	1	1
589	1	1
590	1	1
591	1	1
592	1	1
594	1	1
598	1	1
599	1	1
610	1	1
612	0	1
613	0	1
614	0	1
615	0	1
			MISSING_ELSE
617	1	1
618	1	1
			MISSING_ELSE
620	1	1
621	0	1
622	0	1
623	0	1
624	0	1
			MISSING_ELSE
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
			MISSING_ELSE
643	1	1
644	1	1
645	1	1
646	1	1
			MISSING_ELSE
651	1	1
652	1	1
653	1	1
654	1	1
			MISSING_ELSE
659	1	1
660	1	1
661	1	1
662	1	1
663	1	1
664	1	1
666	1	1
667	1	1
			MISSING_ELSE
673	1	1
674	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
681	1	1
			MISSING_ELSE
686	1	1
687	1	1
688	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
695	1	1
696	1	1
			MISSING_ELSE
703	1	1
704	1	1
705	1	1
706	1	1
			MISSING_ELSE
711	1	1
713	1	1
714	1	1
716	1	1
717	1	1
718	1	1
719	1	1
			MISSING_ELSE
725	1	1
726	1	1
727	1	1
728	1	1
729	1	1
731	1	1
732	1	1
733	1	1
			MISSING_ELSE
739	1	1
740	1	1
741	1	1
742	1	1
			MISSING_ELSE
747	1	1
749	1	1
750	1	1
751	1	1
752	1	1
753	1	1
754	1	1
755	1	1
			MISSING_ELSE
760	1	1
761	1	1
762	1	1
763	1	1
764	1	1
765	1	1
766	1	1
768	1	1
769	1	1
			MISSING_ELSE
776	1	1
777	1	1
778	1	1
779	1	1
780	1	1
			MISSING_ELSE
785	1	1
786	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
807	1	1
808	1	1
809	1	1
812	1	1
813	1	1
814	1	1
815	1	1
			MISSING_ELSE
821	1	1
822	1	1
823	1	1
824	1	1
			MISSING_ELSE
829	1	1
830	1	1
831	1	1
832	1	1
833	1	1
			MISSING_ELSE
838	1	1
839	1	1
840	1	1
841	1	1
842	1	1
844	0	1
845	0	1
846	0	1
848	1	1
849	1	1
850	1	1
			MISSING_ELSE
856	1	1
857	1	1
858	1	1
859	1	1
860	1	1
861	1	1
862	1	1
863	1	1
864	1	1
866	1	1
867	1	1
868	1	1
869	1	1
874	1	1
875	0	1
876	0	1
877	0	1
878	0	1
879	1	1
880	1	1
881	1	1
882	1	1
884	1	1
885	1	1
886	1	1
910	1	1
911	1	1
913	1	1
917	1	1
918	1	1
921	1	1

---

Cond Coverage for Module : i2c_controller_fsm

	Total	Covered	Percent
Conditions	166	153	92.17
Logical	166	153	92.17
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (host_enable_i || (((!host_idle_o)) && ((!host_enable_i))))
             ------1------    --------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T39,T62,T63
1	0	Covered	T1,T2,T9

 LINE       134
 SUB-EXPRESSION (((!host_idle_o)) && ((!host_enable_i)))
                 --------1-------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T39,T62,T63

 LINE       159
 EXPRESSION (stretch_en && ((!scl_i)))
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T10

 LINE       187
 EXPRESSION (stretch_idle_cnt == stretch_cnt_threshold)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       244
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T64,T65,T66

 LINE       279
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T62,T63,T67

 LINE       291
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T69,T44
1	1	Not Covered

 LINE       350
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

 LINE       355
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T10

 LINE       366
 EXPRESSION ((host_idle_o & host_enable_i & ((!sda_i))) | ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i))))
             ---------------------1--------------------   ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T68,T64,T44

 LINE       366
 SUB-EXPRESSION (host_idle_o & host_enable_i & ((!sda_i)))
                 -----1-----   ------2------   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T1,T2,T9
1	1	1	Covered	T68,T64,T44

 LINE       366
 SUB-EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
                 -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T1,T2,T10
1	1	1	Covered	T1,T2,T10

 LINE       366
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       371
 EXPRESSION (unhandled_unexp_nak_i && host_enable_i && (state_q == Idle) && host_nack_handler_timeout_en_i && ((!unhandled_nak_timeout_i)))
             ----------1----------    ------2------    --------3--------    ---------------4--------------    --------------5-------------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T69,T70,T71
1	0	1	1	1	Not Covered
1	1	0	1	1	Covered	T69,T70,T71
1	1	1	0	1	Covered	T72
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T69,T70,T71

 LINE       371
 SUB-EXPRESSION (state_q == Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       440
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Not Covered

 LINE       441
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T44,T61,T66

 LINE       460
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T69,T44,T70
1	0	1	1	Covered	T1,T2,T10
1	1	0	1	Covered	T1,T2,T10
1	1	1	0	Covered	T69,T70,T71
1	1	1	1	Covered	T69,T44,T70

 LINE       462
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Not Covered

 LINE       463
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       482
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T40
1	0	Covered	T2,T10,T40
1	1	Covered	T73

 LINE       483
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       489
 EXPRESSION ((bit_index == '0) && (tcount_q == 16'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T40
1	0	Covered	T2,T10,T40
1	1	Covered	T2,T10,T40

 LINE       489
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       489
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       502
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       509
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       513
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T40
1	0	Covered	T2,T10,T40
1	1	Not Covered

 LINE       514
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T61,T66,T39

 LINE       520
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       551
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T38,T74,T75
1	0	Covered	T68,T69,T44
1	1	Covered	T1,T2,T10

 LINE       599
 EXPRESSION (unhandled_unexp_nak_i || unhandled_nak_timeout_i)
             ----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Not Covered
1	0	Covered	T69,T70,T71

 LINE       610
 EXPRESSION (trans_started && unhandled_nak_cnt_expired)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T69,T70,T71
1	1	Not Covered

 LINE       620
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       634
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       643
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       651
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T76,T77,T78
1	Covered	T1,T2,T10

 LINE       660
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       674
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T44,T41,T79

 LINE       678
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       687
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       691
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       703
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       711
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T10

 LINE       716
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       725
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       739
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       747
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T40
1	0	Covered	T2,T10,T40
1	1	Covered	T44,T41,T79

 LINE       751
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       760
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       763
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       777
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       786
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T40
1	0	Covered	T2,T10,T40
1	1	Covered	T44,T41,T63

 LINE       790
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       799
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       801
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T10,T40
1	Covered	T2,T10,T40

 LINE       821
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       829
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       839
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       861
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T38,T74,T75
1	0	Covered	T68,T69,T44
1	1	Covered	T1,T2,T10

 LINE       874
 EXPRESSION (((!host_enable_i)) && trans_started)
             ---------1--------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T39,T62,T63
1	1	Not Covered

 LINE       879
 EXPRESSION (((!host_enable_i)) || (fmt_fifo_depth_i == 7'b1) || unhandled_unexp_nak_i)
             ---------1--------    -------------2------------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T10
0	0	1	Covered	T69,T70,T71
0	1	0	Covered	T1,T2,T10
1	0	0	Covered	T39,T62,T63

 LINE       879
 SUB-EXPRESSION (fmt_fifo_depth_i == 7'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T10

 LINE       921
 EXPRESSION (stretch_en && (stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i)
             -----1----    ----------------------2---------------------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T10,T40
1	1	0	Covered	T1,T2,T10
1	1	1	Covered	T2,T10,T40

---

FSM Coverage for Module : i2c_controller_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	33	30	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Active	618	Covered	T1,T2,T10
ClockLow	652	Covered	T1,T2,T10
ClockLowAck	692	Covered	T1,T2,T10
ClockPulse	666	Covered	T1,T2,T10
ClockPulseAck	704	Covered	T1,T2,T10
ClockStart	644	Covered	T1,T2,T10
ClockStop	613	Covered	T1,T2,T10
HoldBit	679	Covered	T1,T2,T10
HoldDevAck	717	Covered	T1,T2,T10
HoldStart	635	Covered	T1,T2,T10
HoldStop	830	Covered	T1,T2,T10
HostClockLowAck	764	Covered	T2,T10,T40
HostClockPulseAck	778	Covered	T2,T10,T40
HostHoldBitAck	791	Covered	T2,T10,T40
Idle	844	Covered	T1,T2,T3
PopFmtFifo	731	Covered	T1,T2,T10
ReadClockLow	768	Covered	T2,T10,T40
ReadClockPulse	740	Covered	T2,T10,T40
ReadHoldBit	752	Covered	T2,T10,T40
SetupStart	663	Covered	T1,T2,T10
SetupStop	822	Covered	T1,T2,T10

transitions	Line No.	Covered	Tests
Active->ClockLow	866	Covered	T1,T2,T10
Active->ReadClockLow	858	Covered	T2,T10,T40
Active->SetupStart	862	Covered	T1,T2,T10
ClockLow->ClockPulse	666	Covered	T1,T2,T10
ClockLow->SetupStart	663	Covered	T68,T69,T44
ClockLowAck->ClockPulseAck	704	Covered	T1,T2,T10
ClockPulse->HoldBit	679	Covered	T1,T2,T10
ClockPulseAck->HoldDevAck	717	Covered	T1,T2,T10
ClockStart->ClockLow	652	Covered	T1,T2,T10
ClockStop->SetupStop	822	Covered	T1,T2,T10
HoldBit->ClockLow	695	Covered	T1,T2,T10
HoldBit->ClockLowAck	692	Covered	T1,T2,T10
HoldDevAck->ClockStop	727	Covered	T1,T2,T10
HoldDevAck->PopFmtFifo	731	Covered	T1,T2,T10
HoldStart->ClockStart	644	Covered	T1,T2,T10
HoldStop->Idle	844	Not Covered
HoldStop->PopFmtFifo	848	Covered	T1,T2,T10
HostClockLowAck->HostClockPulseAck	778	Covered	T2,T10,T40
HostClockPulseAck->HostHoldBitAck	791	Covered	T2,T10,T40
HostHoldBitAck->ClockStop	803	Covered	T2,T10,T40
HostHoldBitAck->PopFmtFifo	807	Covered	T80,T64,T69
HostHoldBitAck->ReadClockLow	812	Covered	T2,T10,T40
Idle->Active	618	Covered	T1,T2,T10
Idle->ClockStop	613	Not Covered
PopFmtFifo->Active	884	Covered	T1,T2,T10
PopFmtFifo->ClockStop	876	Not Covered
PopFmtFifo->Idle	880	Covered	T1,T2,T10
ReadClockLow->ReadClockPulse	740	Covered	T2,T10,T40
ReadClockPulse->ReadHoldBit	752	Covered	T2,T10,T40
ReadHoldBit->HostClockLowAck	764	Covered	T2,T10,T40
ReadHoldBit->ReadClockLow	768	Covered	T2,T10,T40
SetupStart->HoldStart	635	Covered	T1,T2,T10
SetupStop->HoldStop	830	Covered	T1,T2,T10

---

Branch Coverage for Module : i2c_controller_fsm

	Line No.	Total	Covered	Percent
Branches		170	158	92.94
IF	119	14	13	92.86
IF	144	2	2	100.00
IF	157	3	3	100.00
IF	184	4	4	100.00
IF	200	4	3	75.00
IF	219	4	4	100.00
IF	232	4	4	100.00
IF	243	3	3	100.00
IF	250	4	4	100.00
IF	263	2	2	100.00
IF	277	5	5	100.00
IF	289	5	4	80.00
IF	301	2	2	100.00
IF	348	4	4	100.00
CASE	387	48	44	91.67
CASE	594	60	55	91.67
IF	910	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	119	if (load_tcount)
-2-:	120	case (tcount_sel)
-3-:	134	if ((host_enable_i || ((!host_idle_o) && (!host_enable_i))))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T1,T2,T10
1	tHoldStart	-	Covered	T1,T2,T10
1	tClockStart	-	Covered	T1,T2,T10
1	tClockLow	-	Covered	T1,T2,T10
1	tClockPulse	-	Covered	T1,T2,T10
1	tClockHigh	-	Covered	T1,T2,T10
1	tHoldBit	-	Covered	T1,T2,T10
1	tClockStop	-	Covered	T1,T2,T10
1	tSetupStop	-	Covered	T1,T2,T10
1	tHoldStop	-	Covered	T1,T2,T10
1	tNoDelay	-	Covered	T1,T2,T10
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T9
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if ((!rst_ni))
-2-:	159	if ((stretch_en && (!scl_i)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	184	if ((!rst_ni))
-2-:	187	if ((stretch_idle_cnt == stretch_cnt_threshold))
-3-:	189	if ((!stretch_en))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T10
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T10

	LineNo.	Expression
-1-:	200	if ((!rst_ni))
-2-:	203	if (incr_nak_cnt)
-3-:	206	if ((unhandled_nak_cnt > host_nack_handler_timeout_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Not Covered
0	1	0	Covered	T69,T70,T71
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	219	if ((!rst_ni))
-2-:	221	if (bit_clr)
-3-:	223	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T10
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (read_byte_clr)
-3-:	236	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T10,T40
0	0	1	Covered	T2,T10,T40
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if ((!fmt_flag_read_bytes_i))
-2-:	244	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T64,T65,T66
0	0	Covered	T2,T10,T40

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (byte_clr)
-3-:	254	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T10,T40
0	0	1	Covered	T2,T10,T40
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	277	if ((!rst_ni))
-2-:	279	if ((trans_started && (!host_enable_i)))
-3-:	281	if (log_start)
-4-:	283	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T62,T63,T67
0	0	1	-	Covered	T1,T2,T10
0	0	0	1	Covered	T1,T2,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	if ((!rst_ni))
-2-:	291	if ((pend_restart && (!host_enable_i)))
-3-:	293	if (req_restart)
-4-:	295	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T68,T69,T44
0	0	0	1	Covered	T1,T2,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	348	if ((!rst_ni))
-2-:	350	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	355	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T10
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	387	case (state_q)
-2-:	393	if (trans_started)
-3-:	411	if (log_start)
-4-:	427	if (pend_restart)
-5-:	440	if ((scl_i_q && (!scl_i)))
-6-:	441	if ((sda_i_q != sda_i))
-7-:	460	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	462	if ((scl_i_q && (!scl_i)))
-9-:	463	if ((sda_i_q != sda_i))
-10-:	482	if ((scl_i_q && (!scl_i)))
-11-:	483	if ((sda_i_q != sda_i))
-12-:	489	if (((bit_index == '0) && (tcount_q == 16'b1)))
-13-:	501	if (fmt_flag_read_continue_i)
-14-:	502	if ((byte_index == 9'b1))
-15-:	508	if (fmt_flag_read_continue_i)
-16-:	509	if ((byte_index == 9'b1))
-17-:	513	if ((scl_i_q && (!scl_i)))
-18-:	514	if ((sda_i_q != sda_i))
-19-:	519	if (fmt_flag_read_continue_i)
-20-:	520	if ((byte_index == 9'b1))
-21-:	556	if (fmt_flag_stop_after_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T71
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T68,T69,T44
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T61,T66
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T69,T44,T70
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T73
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T80,T64,T69
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T80,T64,T69
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T10,T40
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T10,T40
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T10,T40
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T61,T66,T39
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T2,T10,T40
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T80,T64,T69
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T10,T40
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T10,T40
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T10
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	594	case (state_q)
-2-:	598	if (host_enable_i)
-3-:	599	if ((unhandled_unexp_nak_i || unhandled_nak_timeout_i))
-4-:	610	if ((trans_started && unhandled_nak_cnt_expired))
-5-:	617	if (fmt_fifo_rvalid_i)
-6-:	620	if ((trans_started && (!host_enable_i)))
-7-:	634	if ((tcount_q == 16'b1))
-8-:	643	if ((tcount_q == 16'b1))
-9-:	651	if ((tcount_q == 16'b1))
-10-:	660	if ((tcount_q == 16'b1))
-11-:	662	if (pend_restart)
-12-:	674	if (((!scl_i) && stretch_predict_cnt_expired))
-13-:	678	if ((tcount_q == 16'b1))
-14-:	687	if ((tcount_q == 16'b1))
-15-:	691	if ((bit_index == '0))
-16-:	703	if ((tcount_q == 16'b1))
-17-:	711	if (((!scl_i) && stretch_predict_cnt_expired))
-18-:	716	if ((tcount_q == 16'b1))
-19-:	725	if ((tcount_q == 16'b1))
-20-:	726	if (fmt_flag_stop_after_i)
-21-:	739	if ((tcount_q == 16'b1))
-22-:	747	if (((!scl_i) && stretch_predict_cnt_expired))
-23-:	751	if ((tcount_q == 16'b1))
-24-:	760	if ((tcount_q == 16'b1))
-25-:	763	if ((bit_index == '0))
-26-:	777	if ((tcount_q == 16'b1))
-27-:	786	if (((!scl_i) && stretch_predict_cnt_expired))
-28-:	790	if ((tcount_q == 16'b1))
-29-:	799	if ((tcount_q == 16'b1))
-30-:	801	if ((byte_index == 9'b1))
-31-:	802	if (fmt_flag_stop_after_i)
-32-:	821	if ((tcount_q == 16'b1))
-33-:	829	if ((tcount_q == 16'b1))
-34-:	839	if ((tcount_q == 16'b1))
-35-:	842	if (auto_stop_q)
-36-:	856	if (fmt_flag_read_bytes_i)
-37-:	861	if ((fmt_flag_start_before_i && (!trans_started)))
-38-:	874	if (((!host_enable_i) && trans_started))
-39-:	879	if ((((!host_enable_i) || (fmt_fifo_depth_i == 7'b1)) || unhandled_unexp_nak_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	Status	Tests
Idle	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T69,T70,T71
Idle	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
Idle	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T9
Idle	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
SetupStart	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldStart	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldStart	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockStart	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockStart	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T76,T77,T78
ClockLow	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T68,T69,T44
ClockLow	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockLow	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulse	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T41,T79
ClockPulse	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulse	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T41,T79
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T41,T63
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Covered	T80,T64,T69
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T40
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T10
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T10
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T10
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T10
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	Not Covered
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T1,T2,T10
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T10
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T10,T40
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T10
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T10
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T10
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	910	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_controller_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SclOutputGlitch_A	389780304	4898194	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389780304	4898194	0	0
T1	15099	730	0	0
T2	343188	17580	0	0
T3	89998	0	0	0
T4	936	0	0	0
T5	71872	0	0	0
T6	260947	0	0	0
T7	64343	0	0	0
T8	176295	0	0	0
T9	49009	0	0	0
T10	320855	17580	0	0
T40	0	3202	0	0
T44	0	49502	0	0
T59	0	784	0	0
T64	0	6988	0	0
T68	0	500	0	0
T69	0	656	0	0
T80	0	5586	0	0