Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

161977

1

T6

2

T8

100

T84

181

ack

14041

1

T3

39

T6

5

T8

28

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	679	1			T3	1		T8	1		T84	3
high	36333	1			T3	3		T8	23		T40	1
med	65625	1			T3	8		T6	3		T8	50
sml	72717	1			T3	27		T6	4		T8	54
all_zero	664	1			T84	1		T75	1		T105	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88132

1

T3

19

T6

2

T8

60

auto[1]

87886

1

T3

20

T6

5

T8

68

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121096

1

T3

29

T6

6

T8

105

auto[1]

54922

1

T3

10

T6

1

T8

23

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168700

1

T3

15

T6

6

T8

117

auto[1]

7318

1

T3

24

T6

1

T8

11

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166323

1

T3

24

T6

3

T8

105

auto[1]

9695

1

T3

15

T6

4

T8

23

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167140

1

T3

25

T6

4

T8

106

auto[1]

8878

1

T3

14

T6

3

T8

22

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88132

1

T3

19

T6

2

T8

60

auto[1]

87886

1

T3

20

T6

5

T8

68

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121096

1

T3

29

T6

6

T8

105

auto[1]

54922

1

T3

10

T6

1

T8

23

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168700

1

T3

15

T6

6

T8

117

auto[1]

7318

1

T3

24

T6

1

T8

11

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166323

1

T3

24

T6

3

T8

105

auto[1]

9695

1

T3

15

T6

4

T8

23

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167140

1

T3

25

T6

4

T8

106

auto[1]

8878

1

T3

14

T6

3

T8

22

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T181

1

T230

1

T231

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T8

1

T232

1

T233

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T234

1

T235

1

T236

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

290

1

T41

4

T63

1

T43

5

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

149

1

T8

1

T41

3

T63

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

163

1

T8

1

T85

2

T41

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

542

1

T8

2

T70

1

T41

6

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

284

1

T8

2

T41

3

T42

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

261

1

T85

2

T41

4

T63

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

539

1

T8

4

T75

2

T85

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

255

1

T41

7

T43

3

T237

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

257

1

T41

5

T43

2

T51

5

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T173

1

T238

1

T239

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T97

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T173

1

T240

1

T177

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	51935	1			T8	26		T84	58		T70	11
write_address_byte	9695	1			T3	15		T6	4		T8	23
read_with_ack	2002	1			T3	10		T39	15		T70	4
read_with_nack	5316	1			T3	14		T6	1		T8	11
stop_byte	8878	1			T3	14		T6	3		T8	22
write_address_byte_nak	4970	1			T6	2		T8	16		T70	11
data_byte_nack	161977	1			T6	2		T8	100		T84	181
stop_byte_nack	5406	1			T8	14		T84	18		T70	4
nakok_byte_nack	80763	1			T6	2		T8	55		T84	82
nakok_addr_byte_nack	2465	1			T6	2		T8	10		T70	5