Group : i2c_env_pkg::i2c_interrupts_cg
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Group : i2c_env_pkg::i2c_interrupts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.interrupts_cg 100.00 1 100 1 64 64




Group Instance : i2c_env_pkg.interrupts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.interrupts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 0 45 100.00


Variables for Group Instance i2c_env_pkg.interrupts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_stretch 2 0 2 100.00 100 1 1 2
cp_acq_stretch_test 1 0 1 100.00 100 1 1 2
cp_acq_threshold 2 0 2 100.00 100 1 1 2
cp_acq_threshold_test 1 0 1 100.00 100 1 1 2
cp_cmd_complete 2 0 2 100.00 100 1 1 2
cp_cmd_complete_test 1 0 1 100.00 100 1 1 2
cp_fmt_threshold 2 0 2 100.00 100 1 1 2
cp_fmt_threshold_test 1 0 1 100.00 100 1 1 2
cp_host_timeout 2 0 2 100.00 100 1 1 2
cp_host_timeout_test 1 0 1 100.00 100 1 1 2
cp_nak 2 0 2 100.00 100 1 1 2
cp_nak_test 1 0 1 100.00 100 1 1 2
cp_rx_overflow 2 0 2 100.00 100 1 1 2
cp_rx_overflow_test 1 0 1 100.00 100 1 1 2
cp_rx_threshold 2 0 2 100.00 100 1 1 2
cp_rx_threshold_test 1 0 1 100.00 100 1 1 2
cp_scl_interference 2 0 2 100.00 100 1 1 2
cp_scl_interference_test 1 0 1 100.00 100 1 1 2
cp_sda_interference 2 0 2 100.00 100 1 1 2
cp_sda_interference_test 1 0 1 100.00 100 1 1 2
cp_sda_unstable 2 0 2 100.00 100 1 1 2
cp_sda_unstable_test 1 0 1 100.00 100 1 1 2
cp_stretch_timeout 2 0 2 100.00 100 1 1 2
cp_stretch_timeout_test 1 0 1 100.00 100 1 1 2
cp_tx_stretch 2 0 2 100.00 100 1 1 2
cp_tx_stretch_test 1 0 1 100.00 100 1 1 2
cp_tx_threshold 2 0 2 100.00 100 1 1 2
cp_tx_threshold_test 1 0 1 100.00 100 1 1 2
cp_unexp_stop 2 0 2 100.00 100 1 1 2
cp_unexp_stop_test 1 0 1 100.00 100 1 1 2


Summary for Variable cp_acq_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_stretch

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357913 1 T1 2 T2 3 T3 133
auto[1] 354985 1 T1 1 T2 1 T3 116



Summary for Variable cp_acq_stretch_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_acq_stretch_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 322 1 T41 4 T51 3 T69 6



Summary for Variable cp_acq_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357864 1 T1 1 T2 3 T3 141
auto[1] 354918 1 T1 2 T2 1 T3 108



Summary for Variable cp_acq_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_acq_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 340 1 T41 12 T51 6 T69 6



Summary for Variable cp_cmd_complete

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_cmd_complete

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357829 1 T1 2 T2 2 T3 134
auto[1] 354910 1 T1 1 T2 2 T3 115



Summary for Variable cp_cmd_complete_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_cmd_complete_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 315 1 T41 8 T51 7 T69 4



Summary for Variable cp_fmt_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmt_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 355982 1 T1 2 T2 3 T3 112
auto[1] 353388 1 T1 1 T2 1 T3 137



Summary for Variable cp_fmt_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_fmt_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 299 1 T41 9 T51 4 T69 6



Summary for Variable cp_host_timeout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_host_timeout

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357546 1 T1 1 T2 4 T3 125
auto[1] 355291 1 T1 2 T3 124 T4 1



Summary for Variable cp_host_timeout_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_host_timeout_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 308 1 T41 5 T51 5 T69 9



Summary for Variable cp_nak

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_nak

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 358058 1 T1 2 T2 2 T3 125
auto[1] 354722 1 T1 1 T2 2 T3 124



Summary for Variable cp_nak_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_nak_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 318 1 T41 4 T51 11 T69 4



Summary for Variable cp_rx_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_overflow

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 356923 1 T1 3 T2 4 T3 143
auto[1] 355842 1 T3 106 T4 1 T5 1



Summary for Variable cp_rx_overflow_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_rx_overflow_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 320 1 T41 8 T51 3 T69 11



Summary for Variable cp_rx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 356825 1 T1 1 T2 2 T3 134
auto[1] 356042 1 T1 2 T2 2 T3 115



Summary for Variable cp_rx_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_rx_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 316 1 T41 5 T51 9 T69 7



Summary for Variable cp_scl_interference

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_scl_interference

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 356949 1 T1 3 T2 2 T3 123
auto[1] 352577 1 T2 2 T3 126 T4 2



Summary for Variable cp_scl_interference_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_scl_interference_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 323 1 T41 6 T51 4 T69 4



Summary for Variable cp_sda_interference

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sda_interference

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 355468 1 T1 2 T2 1 T3 124
auto[1] 353856 1 T1 1 T2 3 T3 125



Summary for Variable cp_sda_interference_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_sda_interference_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 323 1 T41 7 T51 6 T69 4



Summary for Variable cp_sda_unstable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sda_unstable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 356229 1 T1 3 T2 3 T3 137
auto[1] 353188 1 T2 1 T3 112 T4 1



Summary for Variable cp_sda_unstable_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_sda_unstable_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 326 1 T41 7 T51 6 T69 7



Summary for Variable cp_stretch_timeout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_stretch_timeout

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 355481 1 T1 2 T2 3 T3 116
auto[1] 353933 1 T1 1 T2 1 T3 133



Summary for Variable cp_stretch_timeout_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_stretch_timeout_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 316 1 T41 7 T51 4 T69 4



Summary for Variable cp_tx_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_stretch

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357672 1 T1 3 T2 3 T3 120
auto[1] 355197 1 T2 1 T3 129 T6 31



Summary for Variable cp_tx_stretch_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_tx_stretch_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 289 1 T41 8 T51 9 T69 2



Summary for Variable cp_tx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 355254 1 T1 2 T2 3 T3 120
auto[1] 354191 1 T1 1 T2 1 T3 129



Summary for Variable cp_tx_threshold_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_tx_threshold_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 311 1 T41 8 T51 7 T69 10



Summary for Variable cp_unexp_stop

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unexp_stop

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357510 1 T1 2 T2 1 T3 123
auto[1] 355325 1 T1 1 T2 3 T3 126



Summary for Variable cp_unexp_stop_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for cp_unexp_stop_test

Excluded/Illegal bins
NAMECOUNTSTATUS
dis 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 324 1 T41 7 T51 6 T69 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%