Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34703914	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8835547

1

T1

127

T2

50

T3

3785

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	42692386	1			T1	345		T2	9727		T3	12422
values[0x0]	423935	1			T1	77		T2	67		T3	370
values[0x1]	423140	1			T1	84		T2	57		T3	361

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24860429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18679032

1

T1

253

T2

3746

T3

6400

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	147932	1			T1	2		T2	37		T3	52
valid_sources[0x01]	157138	1			T1	1		T2	44		T3	46
valid_sources[0x02]	157313	1			T2	47		T3	65		T4	4
valid_sources[0x03]	159198	1			T1	4		T2	48		T3	38
valid_sources[0x04]	176344	1			T1	1		T2	44		T3	61
valid_sources[0x05]	160537	1			T1	1		T2	39		T3	49
valid_sources[0x06]	162637	1			T1	2		T2	33		T3	51
valid_sources[0x07]	152270	1			T1	7		T2	38		T3	59
valid_sources[0x08]	157285	1			T1	2		T2	48		T3	39
valid_sources[0x09]	167901	1			T2	43		T3	58		T4	6
valid_sources[0x0a]	165135	1			T1	4		T2	48		T3	66
valid_sources[0x0b]	159542	1			T1	3		T2	43		T3	50
valid_sources[0x0c]	156653	1			T2	45		T3	42		T4	8
valid_sources[0x0d]	165206	1			T1	3		T2	43		T3	61
valid_sources[0x0e]	160381	1			T1	6		T2	34		T3	49
valid_sources[0x0f]	159383	1			T1	5		T2	42		T3	41
valid_sources[0x10]	157037	1			T1	5		T2	31		T3	49
valid_sources[0x11]	164228	1			T2	31		T3	45		T4	6
valid_sources[0x12]	150707	1			T1	3		T2	47		T3	50
valid_sources[0x13]	708209	1			T1	1		T2	39		T3	66
valid_sources[0x14]	192311	1			T2	33		T3	61		T4	6
valid_sources[0x15]	168029	1			T1	4		T2	47		T3	59
valid_sources[0x16]	156967	1			T1	5		T2	54		T3	46
valid_sources[0x17]	151972	1			T1	3		T2	36		T3	49
valid_sources[0x18]	252539	1			T1	6		T2	27		T3	59
valid_sources[0x19]	158664	1			T1	4		T2	39		T3	36
valid_sources[0x1a]	157989	1			T1	4		T2	39		T3	46
valid_sources[0x1b]	165769	1			T1	2		T2	33		T3	51
valid_sources[0x1c]	150237	1			T2	47		T3	57		T4	2
valid_sources[0x1d]	183379	1			T1	2		T2	52		T3	65
valid_sources[0x1e]	154269	1			T1	7		T2	55		T3	55
valid_sources[0x1f]	172471	1			T1	2		T2	52		T3	44
valid_sources[0x20]	153585	1			T1	3		T2	40		T3	54
valid_sources[0x21]	176381	1			T1	1		T2	34		T3	39
valid_sources[0x22]	156183	1			T1	3		T2	42		T3	52
valid_sources[0x23]	161803	1			T2	36		T3	49		T4	4
valid_sources[0x24]	247085	1			T1	4		T2	33		T3	62
valid_sources[0x25]	156147	1			T2	41		T3	58		T4	8
valid_sources[0x26]	200553	1			T2	42		T3	55		T4	4
valid_sources[0x27]	150485	1			T2	56		T3	53		T4	2
valid_sources[0x28]	155981	1			T1	1		T2	44		T3	53
valid_sources[0x29]	158533	1			T1	5		T2	41		T3	45
valid_sources[0x2a]	160453	1			T1	1		T2	34		T3	53
valid_sources[0x2b]	275731	1			T1	3		T2	37		T3	45
valid_sources[0x2c]	151205	1			T1	2		T2	31		T3	32
valid_sources[0x2d]	155932	1			T1	2		T2	37		T3	59
valid_sources[0x2e]	161353	1			T1	3		T2	40		T3	57
valid_sources[0x2f]	153864	1			T1	2		T2	25		T3	41
valid_sources[0x30]	150589	1			T2	42		T3	56		T4	3
valid_sources[0x31]	384951	1			T1	1		T2	42		T3	47
valid_sources[0x32]	162247	1			T1	2		T2	31		T3	47
valid_sources[0x33]	157445	1			T1	1		T2	39		T3	46
valid_sources[0x34]	153678	1			T1	3		T2	47		T3	49
valid_sources[0x35]	157916	1			T1	4		T2	36		T3	63
valid_sources[0x36]	170832	1			T2	57		T3	53		T4	8
valid_sources[0x37]	161365	1			T1	1		T2	31		T3	55
valid_sources[0x38]	159072	1			T1	4		T2	40		T3	64
valid_sources[0x39]	178475	1			T2	44		T3	56		T4	4
valid_sources[0x3a]	164267	1			T2	38		T3	55		T4	6
valid_sources[0x3b]	159828	1			T2	24		T3	55		T4	7
valid_sources[0x3c]	161426	1			T1	1		T2	45		T3	49
valid_sources[0x3d]	172321	1			T2	29		T3	40		T4	2
valid_sources[0x3e]	162549	1			T1	9		T2	42		T3	57
valid_sources[0x3f]	190699	1			T1	1		T2	29		T3	55
valid_sources[0x40]	171193	1			T1	5		T2	44		T3	59
valid_sources[0x41]	151790	1			T1	2		T2	35		T3	53
valid_sources[0x42]	148431	1			T1	2		T2	35		T3	49
valid_sources[0x43]	170300	1			T1	3		T2	42		T3	55
valid_sources[0x44]	157834	1			T1	6		T2	30		T3	50
valid_sources[0x45]	153712	1			T1	8		T2	33		T3	63
valid_sources[0x46]	171942	1			T1	1		T2	40		T3	62
valid_sources[0x47]	165922	1			T1	1		T2	27		T3	47
valid_sources[0x48]	161288	1			T2	33		T3	58		T4	10
valid_sources[0x49]	169663	1			T2	34		T3	62		T4	7
valid_sources[0x4a]	154423	1			T1	4		T2	42		T3	47
valid_sources[0x4b]	219438	1			T1	6		T2	37		T3	51
valid_sources[0x4c]	183534	1			T2	58		T3	51		T4	8
valid_sources[0x4d]	172060	1			T1	4		T2	34		T3	43
valid_sources[0x4e]	154160	1			T1	4		T2	36		T3	61
valid_sources[0x4f]	151957	1			T1	1		T2	49		T3	48
valid_sources[0x50]	158183	1			T2	45		T3	61		T4	2
valid_sources[0x51]	161641	1			T1	1		T2	36		T3	50
valid_sources[0x52]	163632	1			T2	44		T3	51		T4	5
valid_sources[0x53]	248451	1			T2	41		T3	41		T4	3
valid_sources[0x54]	158171	1			T2	50		T3	60		T4	5
valid_sources[0x55]	154010	1			T2	46		T3	50		T4	7
valid_sources[0x56]	178350	1			T1	1		T2	33		T3	37
valid_sources[0x57]	154467	1			T2	28		T3	50		T4	2
valid_sources[0x58]	159267	1			T1	2		T2	35		T3	45
valid_sources[0x59]	154330	1			T1	1		T2	39		T3	59
valid_sources[0x5a]	345825	1			T1	1		T2	45		T3	40
valid_sources[0x5b]	163989	1			T1	1		T2	39		T3	48
valid_sources[0x5c]	162242	1			T1	1		T2	39		T3	44
valid_sources[0x5d]	161032	1			T1	1		T2	34		T3	59
valid_sources[0x5e]	200671	1			T2	42		T3	51		T4	5
valid_sources[0x5f]	152546	1			T2	40		T3	49		T4	5
valid_sources[0x60]	170705	1			T2	40		T3	48		T4	4
valid_sources[0x61]	163480	1			T1	6		T2	38		T3	47
valid_sources[0x62]	155282	1			T1	4		T2	45		T3	50
valid_sources[0x63]	152915	1			T1	3		T2	46		T3	47
valid_sources[0x64]	161193	1			T1	2		T2	39		T3	46
valid_sources[0x65]	154043	1			T1	3		T2	42		T3	40
valid_sources[0x66]	158718	1			T1	3		T2	36		T3	56
valid_sources[0x67]	153330	1			T2	34		T3	48		T4	8
valid_sources[0x68]	153137	1			T1	2		T2	42		T3	44
valid_sources[0x69]	158155	1			T1	4		T2	38		T3	49
valid_sources[0x6a]	198348	1			T1	5		T2	47		T3	55
valid_sources[0x6b]	172243	1			T1	2		T2	46		T3	56
valid_sources[0x6c]	154187	1			T1	2		T2	37		T3	47
valid_sources[0x6d]	198690	1			T1	1		T2	30		T3	45
valid_sources[0x6e]	158303	1			T1	1		T2	33		T3	45
valid_sources[0x6f]	266242	1			T2	35		T3	42		T4	5
valid_sources[0x70]	159054	1			T1	1		T2	27		T3	48
valid_sources[0x71]	155074	1			T1	2		T2	39		T3	43
valid_sources[0x72]	156907	1			T1	2		T2	35		T3	45
valid_sources[0x73]	149559	1			T1	1		T2	29		T3	40
valid_sources[0x74]	158299	1			T1	2		T2	33		T3	53
valid_sources[0x75]	164874	1			T1	3		T2	28		T3	46
valid_sources[0x76]	150667	1			T1	1		T2	25		T3	36
valid_sources[0x77]	155469	1			T1	5		T2	40		T3	42
valid_sources[0x78]	151305	1			T1	1		T2	39		T3	53
valid_sources[0x79]	156491	1			T1	4		T2	45		T3	61
valid_sources[0x7a]	167545	1			T1	3		T2	34		T3	44
valid_sources[0x7b]	154034	1			T1	2		T2	49		T3	45
valid_sources[0x7c]	164295	1			T1	2		T2	27		T3	52
valid_sources[0x7d]	149652	1			T1	2		T2	33		T3	55
valid_sources[0x7e]	158107	1			T1	5		T2	36		T3	36
valid_sources[0x7f]	154563	1			T1	2		T2	35		T3	34
valid_sources[0x80]	156461	1			T2	36		T3	54		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8461800

1

T1

57

T2

9

T3

3342

values[0x0]

all_enables

biggest_size

219778

1

T1

41

T2

22

T3

245

values[0x1]

all_enables

biggest_size

153969

1

T1

29

T2

19

T3

198