Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	403563508	6106	0	0
ctrl_rd_A	403563508	1024	0	0
host_fifo_config_rd_A	403563508	5210	0	0
host_nack_handler_timeout_rd_A	403563508	658	0	0
host_timeout_ctrl_rd_A	403563508	552	0	0
intr_enable_rd_A	403563508	2882	0	0
ovrd_rd_A	403563508	1634	0	0
target_fifo_config_rd_A	403563508	954	0	0
target_id_rd_A	403563508	1006	0	0
target_timeout_ctrl_rd_A	403563508	731	0	0
timeout_ctrl_rd_A	403563508	727	0	0
timing0_rd_A	403563508	808	0	0
timing1_rd_A	403563508	842	0	0
timing2_rd_A	403563508	707	0	0
timing3_rd_A	403563508	797	0	0
timing4_rd_A	403563508	827	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	6106	0	0
T66	1841	4	0	0
T115	3971	66	0	0
T116	6042	163	0	0
T127	14090	1	0	0
T128	7164	306	0	0
T132	10144	256	0	0
T137	3900	131	0	0
T146	1487	7	0	0
T147	1861	4	0	0
T148	1540	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	1024	0	0
T115	3971	5	0	0
T127	14090	141	0	0
T129	11036	8	0	0
T131	7966	58	0	0
T161	3141	18	0	0
T164	2854	12	0	0
T168	2970	6	0	0
T170	3825	52	0	0
T171	7249	87	0	0
T172	2980	35	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	5210	0	0
T54	387751	0	0	0
T69	158279	166	0	0
T82	253076	0	0	0
T89	263571	0	0	0
T114	1551	0	0	0
T117	4157	0	0	0
T122	138296	0	0	0
T123	5450	0	0	0
T124	250116	0	0	0
T125	44155	0	0	0
T173	0	192	0	0
T174	0	189	0	0
T175	0	201	0	0
T176	0	309	0	0
T177	0	198	0	0
T178	0	53	0	0
T179	0	218	0	0
T180	0	250	0	0
T181	0	172	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	658	0	0
T127	14090	117	0	0
T129	11036	8	0	0
T131	7966	77	0	0
T151	2447	2	0	0
T161	3141	8	0	0
T164	2854	6	0	0
T170	3825	23	0	0
T171	7249	103	0	0
T172	2980	9	0	0
T182	1492	8	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	552	0	0
T115	3971	5	0	0
T127	14090	79	0	0
T129	11036	13	0	0
T131	7966	23	0	0
T151	2447	8	0	0
T161	3141	16	0	0
T168	2970	8	0	0
T170	3825	10	0	0
T171	7249	138	0	0
T182	1492	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	2882	0	0
T54	387751	0	0	0
T69	158279	39	0	0
T82	253076	0	0	0
T89	263571	0	0	0
T114	1551	0	0	0
T117	4157	0	0	0
T122	138296	0	0	0
T123	5450	0	0	0
T124	250116	0	0	0
T125	44155	0	0	0
T127	0	532	0	0
T161	0	36	0	0
T181	0	25	0	0
T183	0	16	0	0
T184	0	27	0	0
T185	0	22	0	0
T186	0	32	0	0
T187	0	38	0	0
T188	0	25	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	1634	0	0
T34	84563	0	0	0
T36	1779	14	0	0
T41	116974	0	0	0
T42	204353	0	0	0
T59	205286	0	0	0
T60	7854	0	0	0
T61	521567	0	0	0
T62	5645	0	0	0
T63	34405	0	0	0
T64	134786	0	0	0
T189	0	52	0	0
T190	0	35	0	0
T191	0	63	0	0
T192	0	52	0	0
T193	0	62	0	0
T194	0	54	0	0
T195	0	62	0	0
T196	0	31	0	0
T197	0	26	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	954	0	0
T115	3971	1	0	0
T127	14090	173	0	0
T129	11036	15	0	0
T131	7966	112	0	0
T151	2447	9	0	0
T161	3141	8	0	0
T164	2854	5	0	0
T168	2970	10	0	0
T170	3825	17	0	0
T171	7249	131	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	1006	0	0
T115	3971	8	0	0
T127	14090	185	0	0
T129	11036	6	0	0
T131	7966	101	0	0
T151	2447	11	0	0
T161	3141	33	0	0
T168	2970	15	0	0
T170	3825	22	0	0
T171	7249	110	0	0
T182	1492	12	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	731	0	0
T127	14090	113	0	0
T129	11036	5	0	0
T131	7966	72	0	0
T142	14670	141	0	0
T151	2447	14	0	0
T164	2854	4	0	0
T168	2970	7	0	0
T170	3825	11	0	0
T171	7249	125	0	0
T172	2980	26	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	727	0	0
T127	14090	96	0	0
T129	11036	15	0	0
T131	7966	58	0	0
T151	2447	2	0	0
T161	3141	17	0	0
T164	2854	1	0	0
T168	2970	19	0	0
T170	3825	25	0	0
T171	7249	134	0	0
T172	2980	28	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	808	0	0
T115	3971	2	0	0
T127	14090	122	0	0
T129	11036	3	0	0
T131	7966	39	0	0
T151	2447	12	0	0
T161	3141	42	0	0
T164	2854	11	0	0
T170	3825	13	0	0
T171	7249	114	0	0
T182	1492	8	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	842	0	0
T127	14090	115	0	0
T129	11036	13	0	0
T131	7966	77	0	0
T151	2447	9	0	0
T161	3141	35	0	0
T164	2854	10	0	0
T168	2970	22	0	0
T170	3825	4	0	0
T171	7249	151	0	0
T172	2980	17	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	707	0	0
T127	14090	114	0	0
T129	11036	6	0	0
T131	7966	63	0	0
T142	14670	79	0	0
T151	2447	7	0	0
T164	2854	4	0	0
T168	2970	2	0	0
T170	3825	27	0	0
T171	7249	125	0	0
T172	2980	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	797	0	0
T115	3971	8	0	0
T127	14090	87	0	0
T129	11036	9	0	0
T131	7966	68	0	0
T151	2447	12	0	0
T161	3141	32	0	0
T168	2970	12	0	0
T170	3825	25	0	0
T171	7249	120	0	0
T182	1492	7	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403563508	827	0	0
T127	14090	130	0	0
T129	11036	25	0	0
T131	7966	68	0	0
T142	14670	117	0	0
T151	2447	18	0	0
T161	3141	29	0	0
T164	2854	7	0	0
T168	2970	5	0	0
T170	3825	11	0	0
T171	7249	156	0	0