Unified Coverage Report :: Module :: i2c_target_fsm

Module : i2c_target_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.45	88.43	79.05		81.11	78.65	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_target_fsm	85.45	88.43	79.05		81.11	78.65	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_target_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.45	88.43	79.05		81.11	78.65	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.45	88.43	79.05		81.11	78.65	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.64	97.25	73.63			91.67	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_target_fsm

	Line No.	Total	Covered	Percent
TOTAL		363	321	88.43
ALWAYS	133	8	7	87.50
ALWAYS	147	3	3	100.00
ALWAYS	160	7	7	100.00
ALWAYS	175	5	5	100.00
ALWAYS	186	5	5	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
ALWAYS	203	3	3	100.00
ALWAYS	212	5	5	100.00
ALWAYS	223	7	7	100.00
ALWAYS	247	6	6	100.00
ALWAYS	257	6	6	100.00
ALWAYS	267	6	6	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	289	9	9	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
ALWAYS	310	7	7	100.00
ALWAYS	321	5	5	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
ALWAYS	373	4	4	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
ALWAYS	401	126	106	84.13
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
ALWAYS	716	117	96	82.05
CONT_ASSIGN	1048	1	1	100.00
ALWAYS	1052	3	3	100.00
ALWAYS	1061	3	3	100.00
CONT_ASSIGN	1068	1	1	100.00
CONT_ASSIGN	1069	1	1	100.00
CONT_ASSIGN	1072	1	1	100.00
CONT_ASSIGN	1075	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	0	1
141	1	1
142	1	1
			MISSING_ELSE
147	1	1
148	1	1
150	1	1
160	1	1
161	1	1
162	1	1
164	1	1
165	1	1
166	1	1
168	1	1
175	1	1
176	1	1
177	1	1
178	1	1
180	1	1
186	1	1
187	1	1
188	1	1
190	1	1
192	1	1
196	1	1
197	1	1
198	1	1
199	1	1
203	1	1
204	1	1
206	1	1
212	1	1
213	1	1
214	1	1
216	1	1
217	1	1
223	1	1
224	1	1
225	1	1
226	1	1
228	1	1
229	1	1
230	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
262	1	1
			MISSING_ELSE
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
277	1	1
278	1	1
281	1	1
282	1	1
285	1	1
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
296	2	2
297	1	1
299	1	1
304	1	1
305	1	1
306	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	2	2
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	2	2
			MISSING_ELSE
			MISSING_ELSE
338	1	1
341	1	1
342	1	1
373	1	1
374	1	1
375	1	1
376	1	1
			MISSING_ELSE
390	1	1
394	1	1
397	1	1
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
406	1	1
407	1	1
408	1	1
409	1	1
410	1	1
411	1	1
412	1	1
413	1	1
414	1	1
415	1	1
416	1	1
418	1	1
423	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
437	1	1
438	1	1
439	1	1
443	1	1
444	1	1
446	1	1
447	1	1
448	1	1
449	1	1
			MISSING_ELSE
			MISSING_ELSE
455	1	1
457	1	1
460	0	1
			MISSING_ELSE
465	1	1
466	1	1
470	1	1
471	1	1
475	1	1
476	1	1
479	1	1
480	1	1
484	1	1
486	1	1
			MISSING_ELSE
489	1	1
490	1	1
492	1	1
			==> MISSING_ELSE
498	1	1
502	1	1
503	1	1
507	1	1
510	1	1
514	1	1
517	1	1
521	1	1
524	1	1
525	1	1
527	1	1
			MISSING_ELSE
532	1	1
533	1	1
534	1	1
538	1	1
542	1	1
543	1	1
546	0	1
			MISSING_ELSE
551	1	1
552	1	1
556	1	1
557	1	1
561	1	1
562	1	1
564	1	1
565	1	1
566	1	1
567	1	1
			==> MISSING_ELSE
573	0	1
574	0	1
575	0	1
577	0	1
578	0	1
582	0	1
583	0	1
			==> MISSING_ELSE
589	0	1
590	0	1
591	0	1
596	1	1
597	1	1
598	1	1
600	1	1
601	0	1
605	0	1
606	0	1
607	1	1
608	1	1
609	1	1
610	1	1
612	1	1
			MISSING_ELSE
618	1	1
619	1	1
620	1	1
622	1	1
626	0	1
			MISSING_ELSE
631	1	1
632	1	1
633	1	1
637	1	1
638	1	1
639	1	1
640	1	1
643	1	1
644	0	1
645	0	1
646	0	1
			MISSING_ELSE
652	1	1
653	1	1
654	1	1
675	1	1
676	1	1
681	1	1
682	1	1
683	0	1
685	1	1
687	1	1
688	1	1
689	1	1
			MISSING_ELSE
693	1	1
694	1	1
698	1	1
707	1	1
712	1	1
716	1	1
717	1	1
718	1	1
719	1	1
720	1	1
722	1	1
734	1	1
735	1	1
736	1	1
			MISSING_ELSE
743	1	1
744	1	1
745	1	1
747	1	1
748	1	1
751	1	1
			MISSING_ELSE
757	1	1
759	0	1
760	1	1
761	1	1
763	1	1
765	0	1
772	0	1
773	0	1
776	0	1
780	0	1
			==> MISSING_ELSE
787	2	2
			MISSING_ELSE
791	1	1
792	1	1
793	1	1
794	1	1
			MISSING_ELSE
799	1	1
805	1	1
811	0	1
812	1	1
818	1	1
819	1	1
821	1	1
824	1	1
			==> MISSING_ELSE
830	1	1
831	1	1
833	1	1
838	2	2
			MISSING_ELSE
842	1	1
843	1	1
844	1	1
845	1	1
			MISSING_ELSE
850	1	1
851	1	1
852	1	1
854	1	1
855	1	1
856	1	1
			==> MISSING_ELSE
862	1	1
863	1	1
			MISSING_ELSE
869	1	1
871	1	1
872	1	1
875	1	1
			MISSING_ELSE
883	1	1
887	1	1
888	1	1
889	1	1
890	1	1
			MISSING_ELSE
895	1	1
897	0	1
898	1	1
899	1	1
900	0	1
901	1	1
905	1	1
907	1	1
			==> MISSING_ELSE
913	2	2
			MISSING_ELSE
917	1	1
918	1	1
919	1	1
920	1	1
			MISSING_ELSE
925	1	1
926	1	1
			==> MISSING_ELSE
934	0	1
935	0	1
936	0	1
937	0	1
938	0	1
939	0	1
			==> MISSING_ELSE
945	0	1
946	0	1
			==> MISSING_ELSE
954	1	1
955	0	1
956	1	1
962	1	1
			MISSING_ELSE
968	1	1
969	1	1
970	0	1
971	1	1
978	1	1
979	1	1
980	1	1
983	1	1
			MISSING_ELSE
988	1	1
989	1	1
			MISSING_ELSE
1000	1	1
1001	0	1
1002	1	1
1003	1	1
1004	1	1
1005	1	1
			MISSING_ELSE
1011	1	1
1012	1	1
			MISSING_ELSE
1028	1	1
1037	0	1
1038	1	1
1039	1	1
1040	1	1
1041	1	1
			MISSING_ELSE
1048	1	1
1052	1	1
1053	1	1
1055	1	1
1061	1	1
1062	1	1
1064	1	1
1068	1	1
1069	1	1
1072	1	1
1075	1	1

---

Cond Coverage for Module : i2c_target_fsm

	Total	Covered	Percent
Conditions	148	117	79.05
Logical	148	117	79.05
Non-Logical	0	0
Event	0	0

 LINE       162
 EXPRESSION (((!target_idle_o)) && event_host_timeout_o)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T11,T12,T13

 LINE       165
 EXPRESSION (((!target_idle_o)) && scl_i)
             ---------1--------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       188
 EXPRESSION (auto_ack_load_i && ack_ctrl_stretching)
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Not Covered
1	1	Covered	T5,T9,T10

 LINE       196
 EXPRESSION (((!ack_ctrl_mode_i)) || (auto_ack_cnt_q > '0))
             ----------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T10
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

 LINE       249
 EXPRESSION (start_det_trigger || stop_det_trigger)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       251
 EXPRESSION (start_det_pending || stop_det_pending)
             --------1--------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       261
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || start_det || stop_det_trigger)
             ----------1---------    -----2----    ----3----    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T5
0	0	0	1	Covered	T1,T2,T5
0	0	1	0	Covered	T1,T2,T5
0	1	0	0	Covered	T1,T2,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (((!target_enable_i)) || ((!scl_i)) || stop_det || start_det_trigger)
             ----------1---------    -----2----    ----3---    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T5
0	0	0	1	Covered	T1,T2,T5
0	0	1	0	Covered	T1,T2,T5
0	1	0	0	Covered	T1,T2,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i)))))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       277
 SUB-EXPRESSION ((scl_i_q && scl_i) & (sda_i_q && ((!sda_i))))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       277
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       277
 SUB-EXPRESSION (sda_i_q && ((!sda_i)))
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (target_enable_i && start_det_pending && (ctrl_det_count >= 16'(thd_dat_i)))
             -------1-------    --------2--------    -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       281
 EXPRESSION (target_enable_i && ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i)))
             -------1-------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       281
 SUB-EXPRESSION ((scl_i_q && scl_i) & (((!sda_i_q)) && sda_i))
                 ---------1--------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       281
 SUB-EXPRESSION (scl_i_q && scl_i)
                 ---1---    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       281
 SUB-EXPRESSION (((!sda_i_q)) && sda_i)
                 ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (target_enable_i && stop_det_pending && (ctrl_det_count >= 16'(thd_dat_i)))
             -------1-------    --------2-------    -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       285
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5

 LINE       304
 EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       305
 EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       306
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       314
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       323
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (xfer_for_us_q & rw_bit_q & stop_det & ((!expect_stop)))
             ------1------   ----2---   ----3---   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T14,T15,T16
1	0	1	1	Covered	T1,T5,T9
1	1	0	1	Covered	T1,T2,T5
1	1	1	0	Covered	T1,T2,T5
1	1	1	1	Covered	T17,T18,T19

 LINE       397
 EXPRESSION (((!nack_transaction_q)) && nack_transaction_d)
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       479
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       564
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T5,T9

 LINE       643
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T10
0	1	Not Covered
1	0	Not Covered

 LINE       643
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Not Covered
1	1	Not Covered

 LINE       693
 EXPRESSION (((!acq_fifo_plenty_space)) || ((!can_auto_ack)))
             -------------1------------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T10
1	0	Covered	T20,T21,T22

 LINE       698
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       707
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

 LINE       760
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       799
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       850
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       898
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T5,T9

 LINE       925
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T5,T9

 LINE       945
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       962
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Not Covered

 LINE       988
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T5

 LINE       1000
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T10
0	1	Not Covered
1	0	Not Covered

 LINE       1000
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Not Covered
1	1	Not Covered

 LINE       1011
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T9,T10
1	Covered	T5,T9,T10

 LINE       1028
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Not Covered

 LINE       1048
 EXPRESSION (target_enable_i && ((!target_idle)) && (stop_det | start_det))
             -------1-------    --------2-------    -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       1048
 SUB-EXPRESSION (stop_det | start_det)
                 ----1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       1072
 EXPRESSION (((!target_idle_o)) & (stretch_idle_cnt > host_timeout_i))
             ---------1--------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T11,T12,T13

---

FSM Coverage for Module : i2c_target_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	26	24	92.31	(Not included in score)
Transitions	90	73	81.11
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	918	Covered	T1,T5,T9
AcquireAckPulse	913	Covered	T1,T5,T9
AcquireAckSetup	907	Covered	T1,T5,T9
AcquireAckWait	888	Covered	T1,T5,T9
AcquireByte	824	Covered	T1,T5,T9
AcquireStart	1039	Covered	T1,T2,T5
AddrAckHold	792	Covered	T1,T2,T5
AddrAckPulse	787	Covered	T1,T2,T5
AddrAckSetup	763	Covered	T1,T2,T5
AddrAckWait	745	Covered	T1,T2,T5
AddrRead	735	Covered	T1,T2,T5
Idle	1037	Covered	T1,T2,T3
StretchAcqFull	905	Covered	T5,T9,T10
StretchAcqSetup	1003	Covered	T5,T9,T10
StretchAddr	818	Covered	T20,T21,T22
StretchAddrAck	776	Not Covered
StretchAddrAckSetup	937	Not Covered
StretchTx	831	Covered	T1,T2,T5
StretchTxSetup	978	Covered	T1,T2,T5
TransmitAck	852	Covered	T1,T2,T5
TransmitAckPulse	863	Covered	T1,T2,T5
TransmitHold	843	Covered	T1,T2,T5
TransmitPulse	838	Covered	T1,T2,T5
TransmitSetup	833	Covered	T1,T2,T5
TransmitWait	821	Covered	T1,T2,T5
WaitForStop	751	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	926	Covered	T1,T5,T9
AcquireAckHold->AcquireStart	1039	Covered	T19,T23
AcquireAckHold->Idle	1037	Covered	T19,T23
AcquireAckPulse->AcquireAckHold	918	Covered	T1,T5,T9
AcquireAckPulse->AcquireStart	1039	Covered	T19,T23
AcquireAckPulse->Idle	1037	Covered	T19,T23
AcquireAckSetup->AcquireAckPulse	913	Covered	T1,T5,T9
AcquireAckSetup->AcquireStart	1039	Covered	T19,T23
AcquireAckSetup->Idle	1037	Covered	T19,T23
AcquireAckWait->AcquireAckSetup	907	Covered	T1,T5,T9
AcquireAckWait->AcquireStart	1039	Covered	T19,T23
AcquireAckWait->Idle	1037	Covered	T19,T23
AcquireAckWait->StretchAcqFull	905	Covered	T5,T9,T10
AcquireAckWait->WaitForStop	897	Not Covered
AcquireByte->AcquireAckWait	888	Covered	T1,T5,T9
AcquireByte->AcquireStart	1039	Covered	T1,T5,T9
AcquireByte->Idle	1037	Covered	T1,T5,T9
AcquireStart->AddrRead	735	Covered	T1,T2,T5
AcquireStart->Idle	1037	Covered	T19,T23
AddrAckHold->AcquireByte	824	Covered	T1,T5,T9
AddrAckHold->AcquireStart	1039	Covered	T19,T23
AddrAckHold->Idle	1037	Covered	T19,T23
AddrAckHold->StretchAddr	818	Covered	T20,T21,T22
AddrAckHold->TransmitWait	821	Covered	T1,T2,T5
AddrAckHold->WaitForStop	811	Not Covered
AddrAckPulse->AcquireStart	1039	Covered	T19,T23
AddrAckPulse->AddrAckHold	792	Covered	T1,T2,T5
AddrAckPulse->Idle	1037	Covered	T19,T23
AddrAckSetup->AcquireStart	1039	Covered	T19,T23
AddrAckSetup->AddrAckPulse	787	Covered	T1,T2,T5
AddrAckSetup->Idle	1037	Covered	T19,T23
AddrAckWait->AcquireStart	1039	Covered	T19,T23
AddrAckWait->AddrAckSetup	763	Covered	T1,T2,T5
AddrAckWait->Idle	1037	Covered	T19,T23
AddrAckWait->StretchAddrAck	776	Not Covered
AddrAckWait->WaitForStop	759	Not Covered
AddrRead->AcquireStart	1039	Covered	T24,T25,T19
AddrRead->AddrAckWait	745	Covered	T1,T2,T5
AddrRead->Idle	1037	Covered	T26,T14,T15
AddrRead->WaitForStop	751	Covered	T1,T10,T27
Idle->AcquireStart	1039	Covered	T1,T2,T5
StretchAcqFull->AcquireStart	1039	Covered	T19,T23
StretchAcqFull->Idle	1037	Covered	T19,T23
StretchAcqFull->StretchAcqSetup	1003	Covered	T5,T9,T10
StretchAcqFull->WaitForStop	1001	Not Covered
StretchAcqSetup->AcquireAckSetup	1012	Covered	T5,T9,T10
StretchAcqSetup->AcquireStart	1039	Not Covered
StretchAcqSetup->Idle	1037	Not Covered
StretchAddr->AcquireByte	962	Covered	T20,T21,T22
StretchAddr->AcquireStart	1039	Covered	T19,T23
StretchAddr->Idle	1037	Covered	T19,T23
StretchAddr->StretchTx	962	Not Covered
StretchAddr->WaitForStop	955	Not Covered
StretchAddrAck->AcquireStart	1039	Not Covered
StretchAddrAck->Idle	1037	Not Covered
StretchAddrAck->StretchAddrAckSetup	937	Not Covered
StretchAddrAck->WaitForStop	935	Not Covered
StretchAddrAckSetup->AcquireStart	1039	Not Covered
StretchAddrAckSetup->AddrAckSetup	946	Not Covered
StretchAddrAckSetup->Idle	1037	Not Covered
StretchTx->AcquireStart	1039	Covered	T19,T23
StretchTx->Idle	1037	Covered	T19,T23
StretchTx->StretchTxSetup	978	Covered	T1,T2,T5
StretchTx->WaitForStop	970	Not Covered
StretchTxSetup->AcquireStart	1039	Covered	T19,T23
StretchTxSetup->Idle	1037	Covered	T19,T23
StretchTxSetup->TransmitSetup	989	Covered	T1,T2,T5
TransmitAck->AcquireStart	1039	Covered	T19,T23
TransmitAck->Idle	1037	Covered	T19,T23
TransmitAck->TransmitAckPulse	863	Covered	T1,T2,T5
TransmitAckPulse->AcquireStart	1039	Covered	T19,T28,T23
TransmitAckPulse->Idle	1037	Covered	T19,T23
TransmitAckPulse->TransmitWait	872	Covered	T1,T2,T5
TransmitAckPulse->WaitForStop	875	Covered	T1,T2,T5
TransmitHold->AcquireStart	1039	Covered	T19,T23
TransmitHold->Idle	1037	Covered	T19,T23
TransmitHold->TransmitAck	852	Covered	T1,T2,T5
TransmitHold->TransmitSetup	856	Covered	T1,T2,T5
TransmitPulse->AcquireStart	1039	Covered	T17,T18,T19
TransmitPulse->Idle	1037	Covered	T17,T18,T19
TransmitPulse->TransmitHold	843	Covered	T1,T2,T5
TransmitSetup->AcquireStart	1039	Covered	T19,T23
TransmitSetup->Idle	1037	Covered	T19,T23
TransmitSetup->TransmitPulse	838	Covered	T1,T2,T5
TransmitWait->AcquireStart	1039	Covered	T19,T23
TransmitWait->Idle	1037	Covered	T19,T23
TransmitWait->StretchTx	831	Covered	T1,T2,T5
TransmitWait->TransmitSetup	833	Covered	T1,T2,T5
WaitForStop->AcquireStart	1039	Covered	T1,T2,T5
WaitForStop->Idle	1037	Covered	T1,T2,T5

---

Branch Coverage for Module : i2c_target_fsm

	Line No.	Total	Covered	Percent
Branches		178	140	78.65
IF	134	6	4	66.67
IF	147	2	2	100.00
IF	160	4	4	100.00
IF	175	3	3	100.00
IF	186	3	3	100.00
IF	203	2	2	100.00
IF	212	2	2	100.00
IF	223	2	2	100.00
IF	247	4	4	100.00
IF	257	4	4	100.00
IF	267	4	4	100.00
IF	289	5	5	100.00
IF	310	5	5	100.00
IF	321	4	4	100.00
IF	373	3	3	100.00
CASE	418	44	32	72.73
IF	675	4	3	75.00
CASE	722	69	47	68.12
IF	1028	4	3	75.00
IF	1052	2	2	100.00
IF	1061	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	134	if (load_tcount)
-2-:	135	case (tcount_sel)
-3-:	141	if (target_enable_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupData	-	Covered	T1,T2,T5
1	tHoldData	-	Covered	T1,T2,T5
1	tNoDelay	-	Not Covered
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	147	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	if ((!rst_ni))
-2-:	162	if (((!target_idle_o) && event_host_timeout_o))
-3-:	165	if (((!target_idle_o) && scl_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	175	if ((!rst_ni))
-2-:	177	if (actively_stretching)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	if ((!rst_ni))
-2-:	188	if ((auto_ack_load_i && ack_ctrl_stretching))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T9,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	203	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	212	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	247	if ((!rst_ni))
-2-:	249	if ((start_det_trigger || stop_det_trigger))
-3-:	251	if ((start_det_pending || stop_det_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (start_det_trigger)
-3-:	261	if (((((!target_enable_i) || (!scl_i)) || start_det) || stop_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (stop_det_trigger)
-3-:	271	if (((((!target_enable_i) || (!scl_i)) || stop_det) || start_det_trigger))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	289	if ((!rst_ni))
-2-:	291	if (start_det)
-3-:	293	if ((scl_i_q && (!scl_i)))
-4-:	296	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T5
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	310	if ((!rst_ni))
-2-:	312	if (input_byte_clr)
-3-:	314	if (((!scl_i_q) && scl_i))
-4-:	315	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T5
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if ((!rst_ni))
-2-:	323	if (((!scl_i_q) && scl_i))
-3-:	324	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	373	if ((!rst_ni))
-2-:	375	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	418	case (state_q)
-2-:	446	if (bit_ack)
-3-:	447	if (address_match)
-4-:	457	if (scl_i)
-5-:	479	if ((tcount_q == 16'b1))
-6-:	480	if (nack_transaction_q)
-7-:	484	if ((!stretch_addr))
-8-:	489	if (restart_det_q)
-9-:	525	if ((!scl_i))
-10-:	543	if (scl_i)
-11-:	564	if ((tcount_q == 16'b1))
-12-:	577	if (nack_timeout)
-13-:	600	if (nack_timeout)
-14-:	607	if ((!stretch_addr))
-15-:	609	if (restart_det_q)
-16-:	622	if (nack_timeout)
-17-:	643	if ((nack_timeout || (sw_nack_i && (!can_auto_ack))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
Idle	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T27
AddrRead	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckWait	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckHold	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
AddrAckHold	-	-	-	1	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	1	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAckPulse	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAckPulse	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckHold	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckHold	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	Covered	T20,T21,T22
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	Covered	T21,T29,T30
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T20,T21,T22
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T5
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T9,T10
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	675	if (stop_det)
-2-:	682	if (nack_transaction_q)
-3-:	687	if (start_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T5
0	-	1	Covered	T1,T2,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	722	case (state_q)
-2-:	734	if ((!scl_i))
-3-:	743	if (bit_ack)
-4-:	744	if (address_match)
-5-:	757	if (scl_i)
-6-:	760	if ((tcount_q == 16'b1))
-7-:	761	if ((!nack_addr_after_timeout_i))
-8-:	765	if (nack_transaction_q)
-9-:	773	if (stretch_addr)
-10-:	787	if (scl_i)
-11-:	791	if ((!scl_i))
-12-:	799	if ((tcount_q == 16'b1))
-13-:	805	if (nack_transaction_q)
-14-:	812	if (stretch_addr)
-15-:	819	if (rw_bit_q)
-16-:	830	if (stretch_tx)
-17-:	838	if (scl_i)
-18-:	842	if ((!scl_i))
-19-:	850	if ((tcount_q == 16'b1))
-20-:	851	if (bit_ack)
-21-:	862	if (scl_i)
-22-:	869	if ((!scl_i))
-23-:	871	if (host_ack)
-24-:	887	if (bit_ack)
-25-:	895	if (scl_i)
-26-:	898	if ((tcount_q == 16'b1))
-27-:	899	if (nack_transaction_q)
-28-:	901	if (stretch_rx)
-29-:	913	if (scl_i)
-30-:	917	if ((!scl_i))
-31-:	925	if ((tcount_q == 16'b1))
-32-:	934	if (nack_timeout)
-33-:	936	if ((!stretch_addr))
-34-:	945	if ((tcount_q == 16'b1))
-35-:	954	if (nack_timeout)
-36-:	956	if ((!stretch_addr))
-37-:	962	(rw_bit_q) ? 
-38-:	969	if (nack_timeout)
-39-:	971	if ((!stretch_tx))
-40-:	988	if ((tcount_q == 16'b1))
-41-:	1000	if ((nack_timeout || (sw_nack_i && (!can_auto_ack))))
-42-:	1002	if ((~stretch_rx))
-43-:	1011	if ((tcount_q == 16'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	Status	Tests
Idle	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireStart	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T27
AddrRead	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckWait	-	-	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckSetup	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckSetup	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AddrAckHold	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T9,T10
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T9
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	-	-	Covered	T20,T21,T22
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T20,T21,T22
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T5
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T5
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T5
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T5
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T5,T9,T10
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T5,T9,T10
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T9,T10
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	1028	if (((!target_idle) && (!target_enable_i)))
-2-:	1038	if (start_det)
-3-:	1040	if (stop_det)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1052	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1061	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_target_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	403104103	3974809	0	0
AcqFifoDeepEnough_A	403104103	402928762	0	0
SclOutputGlitch_A	403104103	63475	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403104103	3974809	0	0
T1	76380	325	0	0
T2	22808	109	0	0
T3	131610	0	0	0
T4	12941	0	0	0
T5	101816	1178	0	0
T6	31100	0	0	0
T7	31723	163	0	0
T8	38673	0	0	0
T9	244428	14429	0	0
T10	72208	131	0	0
T31	0	172	0	0
T32	0	298	0	0
T33	0	177	0	0
T34	0	170	0	0

AcqFifoDeepEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403104103	402928762	0	0
T1	76380	76326	0	0
T2	22808	22712	0	0
T3	131610	131530	0	0
T4	12941	12854	0	0
T5	101816	101729	0	0
T6	31100	31028	0	0
T7	31723	31651	0	0
T8	38673	38593	0	0
T9	244428	244354	0	0
T10	72208	72135	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403104103	63475	0	0
T1	76380	8	0	0
T2	22808	41	0	0
T3	131610	0	0	0
T4	12941	0	0	0
T5	101816	83	0	0
T6	31100	0	0	0
T7	31723	52	0	0
T8	38673	0	0	0
T9	244428	103	0	0
T10	72208	54	0	0
T20	0	92	0	0
T21	0	512	0	0
T31	0	24	0	0
T32	0	126	0	0