Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47394120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11389865

1

T1

2184

T2

690

T3

2805

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57871909	1			T1	3240		T2	1132		T3	10700
values[0x0]	456175	1			T1	2085		T2	631		T3	47
values[0x1]	455901	1			T1	2062		T2	666		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33893956	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24890029

1

T1

3381

T2

1084

T3

5079

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	202954	1			T1	31		T2	16		T3	51
valid_sources[0x01]	208687	1			T1	24		T2	10		T3	41
valid_sources[0x02]	213376	1			T1	19		T2	8		T3	44
valid_sources[0x03]	216306	1			T1	23		T2	13		T3	46
valid_sources[0x04]	207017	1			T1	34		T3	53		T4	199
valid_sources[0x05]	200821	1			T1	43		T2	14		T3	50
valid_sources[0x06]	525871	1			T1	19		T2	8		T3	47
valid_sources[0x07]	221895	1			T1	29		T2	8		T3	41
valid_sources[0x08]	203219	1			T1	21		T2	18		T3	36
valid_sources[0x09]	238812	1			T1	28		T2	19		T3	53
valid_sources[0x0a]	226950	1			T1	34		T2	4		T3	39
valid_sources[0x0b]	205162	1			T1	21		T2	14		T3	40
valid_sources[0x0c]	196066	1			T1	31		T2	4		T3	49
valid_sources[0x0d]	229346	1			T1	16		T2	14		T3	46
valid_sources[0x0e]	202468	1			T1	31		T2	16		T3	38
valid_sources[0x0f]	216425	1			T1	19		T2	6		T3	48
valid_sources[0x10]	210562	1			T1	25		T2	7		T3	43
valid_sources[0x11]	216325	1			T1	23		T2	21		T3	39
valid_sources[0x12]	207218	1			T1	30		T2	8		T3	35
valid_sources[0x13]	233217	1			T1	40		T2	9		T3	49
valid_sources[0x14]	295971	1			T1	31		T2	5		T3	34
valid_sources[0x15]	205121	1			T1	40		T2	4		T3	42
valid_sources[0x16]	203156	1			T1	33		T2	3		T3	47
valid_sources[0x17]	199723	1			T1	18		T2	34		T3	39
valid_sources[0x18]	213244	1			T1	24		T2	6		T3	42
valid_sources[0x19]	284970	1			T1	32		T2	5		T3	45
valid_sources[0x1a]	211048	1			T1	29		T2	12		T3	53
valid_sources[0x1b]	439852	1			T1	39		T2	13		T3	51
valid_sources[0x1c]	213260	1			T1	25		T3	45		T4	265
valid_sources[0x1d]	198377	1			T1	43		T2	2		T3	36
valid_sources[0x1e]	203284	1			T1	40		T2	1		T3	43
valid_sources[0x1f]	207451	1			T1	38		T2	9		T3	43
valid_sources[0x20]	476309	1			T1	27		T2	14		T3	45
valid_sources[0x21]	221580	1			T1	23		T2	13		T3	46
valid_sources[0x22]	204237	1			T1	26		T2	17		T3	41
valid_sources[0x23]	280431	1			T1	30		T2	15		T3	42
valid_sources[0x24]	210458	1			T1	34		T2	25		T3	42
valid_sources[0x25]	226989	1			T1	29		T2	10		T3	58
valid_sources[0x26]	207326	1			T1	28		T2	23		T3	54
valid_sources[0x27]	207368	1			T1	31		T2	1		T3	42
valid_sources[0x28]	206899	1			T1	22		T2	22		T3	32
valid_sources[0x29]	219452	1			T1	27		T2	24		T3	36
valid_sources[0x2a]	201515	1			T1	27		T2	6		T3	50
valid_sources[0x2b]	207721	1			T1	17		T2	6		T3	41
valid_sources[0x2c]	210470	1			T1	29		T2	10		T3	38
valid_sources[0x2d]	232939	1			T1	16		T2	2		T3	47
valid_sources[0x2e]	221310	1			T1	33		T2	12		T3	45
valid_sources[0x2f]	206934	1			T1	33		T2	12		T3	42
valid_sources[0x30]	211370	1			T1	30		T2	6		T3	37
valid_sources[0x31]	224365	1			T1	26		T2	11		T3	50
valid_sources[0x32]	209527	1			T1	38		T2	4		T3	49
valid_sources[0x33]	207648	1			T1	22		T2	11		T3	45
valid_sources[0x34]	220251	1			T1	22		T2	13		T3	42
valid_sources[0x35]	222658	1			T1	26		T2	18		T3	36
valid_sources[0x36]	226810	1			T1	33		T2	8		T3	45
valid_sources[0x37]	273814	1			T1	35		T2	6		T3	34
valid_sources[0x38]	217446	1			T1	21		T3	44		T4	275
valid_sources[0x39]	209111	1			T1	23		T2	11		T3	43
valid_sources[0x3a]	204935	1			T1	20		T3	42		T4	243
valid_sources[0x3b]	229669	1			T1	21		T2	1		T3	54
valid_sources[0x3c]	199855	1			T1	17		T2	5		T3	42
valid_sources[0x3d]	227571	1			T1	23		T2	10		T3	40
valid_sources[0x3e]	221765	1			T1	39		T2	18		T3	34
valid_sources[0x3f]	211353	1			T1	35		T2	13		T3	36
valid_sources[0x40]	268415	1			T1	42		T2	3		T3	49
valid_sources[0x41]	210456	1			T1	30		T2	11		T3	51
valid_sources[0x42]	348059	1			T1	32		T2	1		T3	37
valid_sources[0x43]	207540	1			T1	44		T2	10		T3	40
valid_sources[0x44]	218895	1			T1	18		T2	3		T3	38
valid_sources[0x45]	204707	1			T1	30		T2	23		T3	31
valid_sources[0x46]	345297	1			T1	32		T2	3		T3	53
valid_sources[0x47]	204459	1			T1	29		T2	8		T3	44
valid_sources[0x48]	205043	1			T1	26		T2	7		T3	33
valid_sources[0x49]	199695	1			T1	27		T2	13		T3	48
valid_sources[0x4a]	193689	1			T1	23		T2	6		T3	36
valid_sources[0x4b]	207904	1			T1	26		T2	13		T3	49
valid_sources[0x4c]	214232	1			T1	26		T2	7		T3	44
valid_sources[0x4d]	207633	1			T1	45		T2	6		T3	40
valid_sources[0x4e]	215835	1			T1	41		T2	17		T3	41
valid_sources[0x4f]	197828	1			T1	24		T2	22		T3	40
valid_sources[0x50]	205074	1			T1	29		T2	3		T3	43
valid_sources[0x51]	204825	1			T1	18		T2	12		T3	43
valid_sources[0x52]	203730	1			T1	31		T2	7		T3	38
valid_sources[0x53]	215243	1			T1	27		T2	7		T3	35
valid_sources[0x54]	208854	1			T1	27		T2	12		T3	38
valid_sources[0x55]	218107	1			T1	38		T2	3		T3	36
valid_sources[0x56]	210592	1			T1	59		T2	2		T3	43
valid_sources[0x57]	202915	1			T1	36		T2	28		T3	54
valid_sources[0x58]	198463	1			T1	32		T2	12		T3	47
valid_sources[0x59]	221817	1			T1	23		T3	43		T4	266
valid_sources[0x5a]	204375	1			T1	25		T2	5		T3	37
valid_sources[0x5b]	251964	1			T1	18		T2	28		T3	40
valid_sources[0x5c]	204101	1			T1	33		T2	8		T3	32
valid_sources[0x5d]	234249	1			T1	21		T2	6		T3	38
valid_sources[0x5e]	226325	1			T1	25		T2	3		T3	48
valid_sources[0x5f]	210309	1			T1	39		T2	9		T3	48
valid_sources[0x60]	224397	1			T1	44		T2	2		T3	52
valid_sources[0x61]	207571	1			T1	32		T2	7		T3	50
valid_sources[0x62]	207247	1			T1	25		T2	17		T3	35
valid_sources[0x63]	204138	1			T1	26		T2	13		T3	39
valid_sources[0x64]	206596	1			T1	28		T2	1		T3	41
valid_sources[0x65]	225720	1			T1	30		T2	1		T3	37
valid_sources[0x66]	208151	1			T1	23		T2	12		T3	41
valid_sources[0x67]	207603	1			T1	33		T2	21		T3	42
valid_sources[0x68]	324241	1			T1	27		T2	17		T3	39
valid_sources[0x69]	199290	1			T1	36		T2	19		T3	44
valid_sources[0x6a]	213110	1			T1	28		T2	10		T3	41
valid_sources[0x6b]	210255	1			T1	18		T2	3		T3	36
valid_sources[0x6c]	211066	1			T1	33		T2	5		T3	56
valid_sources[0x6d]	192446	1			T1	16		T2	13		T3	38
valid_sources[0x6e]	205032	1			T1	35		T2	5		T3	50
valid_sources[0x6f]	217213	1			T1	30		T2	11		T3	47
valid_sources[0x70]	193746	1			T1	14		T2	9		T3	44
valid_sources[0x71]	202056	1			T1	19		T2	2		T3	39
valid_sources[0x72]	206928	1			T1	34		T2	13		T3	53
valid_sources[0x73]	206501	1			T1	28		T2	3		T3	43
valid_sources[0x74]	211749	1			T1	47		T2	4		T3	44
valid_sources[0x75]	244841	1			T1	18		T2	10		T3	44
valid_sources[0x76]	277398	1			T1	43		T2	6		T3	44
valid_sources[0x77]	199780	1			T1	35		T2	13		T3	44
valid_sources[0x78]	210584	1			T1	30		T2	3		T3	54
valid_sources[0x79]	193448	1			T1	21		T2	6		T3	41
valid_sources[0x7a]	510115	1			T1	35		T2	15		T3	40
valid_sources[0x7b]	194364	1			T1	31		T2	1		T3	44
valid_sources[0x7c]	195226	1			T1	31		T2	5		T3	34
valid_sources[0x7d]	214688	1			T1	35		T2	13		T3	35
valid_sources[0x7e]	217897	1			T1	28		T2	2		T3	45
valid_sources[0x7f]	204145	1			T1	32		T2	3		T3	47
valid_sources[0x80]	206079	1			T1	25		T2	8		T3	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10990448

1

T1

912

T2

331

T3

2766

values[0x0]

all_enables

biggest_size

236026

1

T1

849

T2

245

T3

27

values[0x1]

all_enables

biggest_size

163391

1

T1

423

T2

114

T3

12