Unified Coverage Report :: Module :: i2c_reg_top

Module : i2c_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.70	100.00	98.81			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.70	100.00	98.81			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.70	100.00	98.81			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.74	98.54	97.66	100.00		97.50	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acq_fifo_next_data	66.67	66.67
u_acqdata_abyte	100.00	100.00
u_acqdata_signal	100.00	100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_controller_events_bus_timeout	88.89	100.00	66.67			100.00
u_controller_events_nack	100.00	100.00	100.00			100.00
u_controller_events_unhandled_nack_timeout	88.89	100.00	66.67			100.00
u_ctrl_ack_ctrl_en	100.00	100.00	100.00			100.00
u_ctrl_enablehost	100.00	100.00	100.00			100.00
u_ctrl_enabletarget	100.00	100.00	100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_ctrl_multi_controller_monitor_en	100.00	100.00	100.00			100.00
u_ctrl_nack_addr_after_timeout	100.00	100.00	100.00			100.00
u_fdata0_qe	100.00	100.00				100.00
u_fdata_fbyte	100.00	100.00	100.00			100.00
u_fdata_nakok	100.00	100.00	100.00			100.00
u_fdata_rcont	100.00	100.00	100.00			100.00
u_fdata_readb	100.00	100.00	100.00			100.00
u_fdata_start	100.00	100.00	100.00			100.00
u_fdata_stop	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_acqrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_fmtrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_host_fifo_config0_qe	100.00	100.00				100.00
u_host_fifo_config_fmt_thresh	100.00	100.00	100.00			100.00
u_host_fifo_config_rx_thresh	100.00	100.00	100.00			100.00
u_host_fifo_status_fmtlvl	100.00	100.00
u_host_fifo_status_rxlvl	100.00	100.00
u_host_nack_handler_timeout_en	100.00	100.00	100.00			100.00
u_host_nack_handler_timeout_val	100.00	100.00	100.00			100.00
u_host_timeout_ctrl	100.00	100.00	100.00			100.00
u_intr_enable_acq_stretch	100.00	100.00	100.00			100.00
u_intr_enable_acq_threshold	100.00	100.00	100.00			100.00
u_intr_enable_cmd_complete	100.00	100.00	100.00			100.00
u_intr_enable_controller_halt	100.00	100.00	100.00			100.00
u_intr_enable_fmt_threshold	100.00	100.00	100.00			100.00
u_intr_enable_host_timeout	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_scl_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_interference	100.00	100.00	100.00			100.00
u_intr_enable_sda_unstable	100.00	100.00	100.00			100.00
u_intr_enable_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_enable_tx_stretch	100.00	100.00	100.00			100.00
u_intr_enable_tx_threshold	100.00	100.00	100.00			100.00
u_intr_enable_unexp_stop	100.00	100.00	100.00			100.00
u_intr_state_acq_stretch	62.59	77.78	50.00			60.00
u_intr_state_acq_threshold	62.59	77.78	50.00			60.00
u_intr_state_cmd_complete	100.00	100.00	100.00			100.00
u_intr_state_controller_halt	62.59	77.78	50.00			60.00
u_intr_state_fmt_threshold	62.59	77.78	50.00			60.00
u_intr_state_host_timeout	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_threshold	62.59	77.78	50.00			60.00
u_intr_state_scl_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_interference	100.00	100.00	100.00			100.00
u_intr_state_sda_unstable	100.00	100.00	100.00			100.00
u_intr_state_stretch_timeout	100.00	100.00	100.00			100.00
u_intr_state_tx_stretch	62.59	77.78	50.00			60.00
u_intr_state_tx_threshold	62.59	77.78	50.00			60.00
u_intr_state_unexp_stop	100.00	100.00	100.00			100.00
u_intr_test_acq_stretch	100.00	100.00
u_intr_test_acq_threshold	100.00	100.00
u_intr_test_cmd_complete	100.00	100.00
u_intr_test_controller_halt	100.00	100.00
u_intr_test_fmt_threshold	100.00	100.00
u_intr_test_host_timeout	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_threshold	100.00	100.00
u_intr_test_scl_interference	100.00	100.00
u_intr_test_sda_interference	100.00	100.00
u_intr_test_sda_unstable	100.00	100.00
u_intr_test_stretch_timeout	100.00	100.00
u_intr_test_tx_stretch	100.00	100.00
u_intr_test_tx_threshold	100.00	100.00
u_intr_test_unexp_stop	100.00	100.00
u_ovrd_sclval	100.00	100.00	100.00			100.00
u_ovrd_sdaval	100.00	100.00	100.00			100.00
u_ovrd_txovrden	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_rdata	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ack_ctrl_stretch	100.00	100.00
u_status_acqempty	100.00	100.00
u_status_acqfull	100.00	100.00
u_status_fmtempty	100.00	100.00
u_status_fmtfull	100.00	100.00
u_status_hostidle	100.00	100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_targetidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_target_ack_ctrl_nack	100.00	100.00
u_target_ack_ctrl_nbytes	100.00	100.00
u_target_fifo_config0_qe	100.00	100.00				100.00
u_target_fifo_config_acq_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_tx_thresh	100.00	100.00	100.00			100.00
u_target_fifo_config_txrst_on_cond	100.00	100.00	100.00			100.00
u_target_fifo_status_acqlvl	100.00	100.00
u_target_fifo_status_txlvl	100.00	100.00
u_target_id_address0	100.00	100.00	100.00			100.00
u_target_id_address1	100.00	100.00	100.00			100.00
u_target_id_mask0	100.00	100.00	100.00			100.00
u_target_id_mask1	100.00	100.00	100.00			100.00
u_target_nack_count	81.90	100.00	60.00			85.71
u_target_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_target_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_mode	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_timing0_thigh	100.00	100.00	100.00			100.00
u_timing0_tlow	100.00	100.00	100.00			100.00
u_timing1_t_f	100.00	100.00	100.00			100.00
u_timing1_t_r	100.00	100.00	100.00			100.00
u_timing2_thd_sta	100.00	100.00	100.00			100.00
u_timing2_tsu_sta	100.00	100.00	100.00			100.00
u_timing3_thd_dat	100.00	100.00	100.00			100.00
u_timing3_tsu_dat	100.00	100.00	100.00			100.00
u_timing4_t_buf	100.00	100.00	100.00			100.00
u_timing4_tsu_sto	100.00	100.00	100.00			100.00
u_txdata	100.00	100.00	100.00			100.00
u_txdata0_qe	100.00	100.00				100.00
u_val_scl_rx	66.67	66.67
u_val_sda_rx	66.67	66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
TOTAL		359	359	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	1159	1	1	100.00
CONT_ASSIGN	1174	1	1	100.00
CONT_ASSIGN	1190	1	1	100.00
CONT_ASSIGN	1206	1	1	100.00
CONT_ASSIGN	1222	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1350	1	1	100.00
CONT_ASSIGN	1366	1	1	100.00
CONT_ASSIGN	1382	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1404	1	1	100.00
CONT_ASSIGN	1418	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1834	1	1	100.00
CONT_ASSIGN	1862	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
CONT_ASSIGN	1918	1	1	100.00
CONT_ASSIGN	1946	1	1	100.00
CONT_ASSIGN	1987	1	1	100.00
CONT_ASSIGN	2015	1	1	100.00
CONT_ASSIGN	2043	1	1	100.00
CONT_ASSIGN	2071	1	1	100.00
CONT_ASSIGN	2112	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2209	1	1	100.00
CONT_ASSIGN	2237	1	1	100.00
CONT_ASSIGN	2961	1	1	100.00
CONT_ASSIGN	3079	1	1	100.00
CONT_ASSIGN	3094	1	1	100.00
CONT_ASSIGN	3110	1	1	100.00
ALWAYS	3271	32	32	100.00
CONT_ASSIGN	3305	1	1	100.00
ALWAYS	3309	1	1	100.00
CONT_ASSIGN	3344	1	1	100.00
CONT_ASSIGN	3346	1	1	100.00
CONT_ASSIGN	3348	1	1	100.00
CONT_ASSIGN	3350	1	1	100.00
CONT_ASSIGN	3352	1	1	100.00
CONT_ASSIGN	3354	1	1	100.00
CONT_ASSIGN	3356	1	1	100.00
CONT_ASSIGN	3358	1	1	100.00
CONT_ASSIGN	3360	1	1	100.00
CONT_ASSIGN	3361	1	1	100.00
CONT_ASSIGN	3363	1	1	100.00
CONT_ASSIGN	3365	1	1	100.00
CONT_ASSIGN	3367	1	1	100.00
CONT_ASSIGN	3369	1	1	100.00
CONT_ASSIGN	3371	1	1	100.00
CONT_ASSIGN	3373	1	1	100.00
CONT_ASSIGN	3375	1	1	100.00
CONT_ASSIGN	3377	1	1	100.00
CONT_ASSIGN	3379	1	1	100.00
CONT_ASSIGN	3381	1	1	100.00
CONT_ASSIGN	3383	1	1	100.00
CONT_ASSIGN	3385	1	1	100.00
CONT_ASSIGN	3387	1	1	100.00
CONT_ASSIGN	3389	1	1	100.00
CONT_ASSIGN	3391	1	1	100.00
CONT_ASSIGN	3392	1	1	100.00
CONT_ASSIGN	3394	1	1	100.00
CONT_ASSIGN	3396	1	1	100.00
CONT_ASSIGN	3398	1	1	100.00
CONT_ASSIGN	3400	1	1	100.00
CONT_ASSIGN	3402	1	1	100.00
CONT_ASSIGN	3404	1	1	100.00
CONT_ASSIGN	3406	1	1	100.00
CONT_ASSIGN	3408	1	1	100.00
CONT_ASSIGN	3410	1	1	100.00
CONT_ASSIGN	3412	1	1	100.00
CONT_ASSIGN	3414	1	1	100.00
CONT_ASSIGN	3416	1	1	100.00
CONT_ASSIGN	3418	1	1	100.00
CONT_ASSIGN	3420	1	1	100.00
CONT_ASSIGN	3422	1	1	100.00
CONT_ASSIGN	3423	1	1	100.00
CONT_ASSIGN	3425	1	1	100.00
CONT_ASSIGN	3426	1	1	100.00
CONT_ASSIGN	3428	1	1	100.00
CONT_ASSIGN	3430	1	1	100.00
CONT_ASSIGN	3432	1	1	100.00
CONT_ASSIGN	3434	1	1	100.00
CONT_ASSIGN	3436	1	1	100.00
CONT_ASSIGN	3438	1	1	100.00
CONT_ASSIGN	3439	1	1	100.00
CONT_ASSIGN	3440	1	1	100.00
CONT_ASSIGN	3441	1	1	100.00
CONT_ASSIGN	3443	1	1	100.00
CONT_ASSIGN	3445	1	1	100.00
CONT_ASSIGN	3447	1	1	100.00
CONT_ASSIGN	3449	1	1	100.00
CONT_ASSIGN	3451	1	1	100.00
CONT_ASSIGN	3453	1	1	100.00
CONT_ASSIGN	3454	1	1	100.00
CONT_ASSIGN	3456	1	1	100.00
CONT_ASSIGN	3458	1	1	100.00
CONT_ASSIGN	3460	1	1	100.00
CONT_ASSIGN	3462	1	1	100.00
CONT_ASSIGN	3463	1	1	100.00
CONT_ASSIGN	3465	1	1	100.00
CONT_ASSIGN	3467	1	1	100.00
CONT_ASSIGN	3468	1	1	100.00
CONT_ASSIGN	3470	1	1	100.00
CONT_ASSIGN	3472	1	1	100.00
CONT_ASSIGN	3474	1	1	100.00
CONT_ASSIGN	3475	1	1	100.00
CONT_ASSIGN	3476	1	1	100.00
CONT_ASSIGN	3477	1	1	100.00
CONT_ASSIGN	3479	1	1	100.00
CONT_ASSIGN	3481	1	1	100.00
CONT_ASSIGN	3483	1	1	100.00
CONT_ASSIGN	3484	1	1	100.00
CONT_ASSIGN	3485	1	1	100.00
CONT_ASSIGN	3487	1	1	100.00
CONT_ASSIGN	3489	1	1	100.00
CONT_ASSIGN	3490	1	1	100.00
CONT_ASSIGN	3492	1	1	100.00
CONT_ASSIGN	3494	1	1	100.00
CONT_ASSIGN	3495	1	1	100.00
CONT_ASSIGN	3497	1	1	100.00
CONT_ASSIGN	3499	1	1	100.00
CONT_ASSIGN	3500	1	1	100.00
CONT_ASSIGN	3502	1	1	100.00
CONT_ASSIGN	3504	1	1	100.00
CONT_ASSIGN	3505	1	1	100.00
CONT_ASSIGN	3507	1	1	100.00
CONT_ASSIGN	3509	1	1	100.00
CONT_ASSIGN	3510	1	1	100.00
CONT_ASSIGN	3512	1	1	100.00
CONT_ASSIGN	3514	1	1	100.00
CONT_ASSIGN	3516	1	1	100.00
CONT_ASSIGN	3517	1	1	100.00
CONT_ASSIGN	3519	1	1	100.00
CONT_ASSIGN	3521	1	1	100.00
CONT_ASSIGN	3523	1	1	100.00
CONT_ASSIGN	3525	1	1	100.00
CONT_ASSIGN	3526	1	1	100.00
CONT_ASSIGN	3527	1	1	100.00
CONT_ASSIGN	3529	1	1	100.00
CONT_ASSIGN	3530	1	1	100.00
CONT_ASSIGN	3532	1	1	100.00
CONT_ASSIGN	3533	1	1	100.00
CONT_ASSIGN	3535	1	1	100.00
CONT_ASSIGN	3537	1	1	100.00
CONT_ASSIGN	3538	1	1	100.00
CONT_ASSIGN	3541	1	1	100.00
CONT_ASSIGN	3542	1	1	100.00
CONT_ASSIGN	3544	1	1	100.00
CONT_ASSIGN	3546	1	1	100.00
CONT_ASSIGN	3547	1	1	100.00
CONT_ASSIGN	3548	1	1	100.00
CONT_ASSIGN	3550	1	1	100.00
CONT_ASSIGN	3552	1	1	100.00
CONT_ASSIGN	3553	1	1	100.00
CONT_ASSIGN	3555	1	1	100.00
CONT_ASSIGN	3557	1	1	100.00
CONT_ASSIGN	3559	1	1	100.00
ALWAYS	3563	32	32	100.00
ALWAYS	3599	122	122	100.00
CONT_ASSIGN	3825	0	0
CONT_ASSIGN	3833	1	1	100.00
CONT_ASSIGN	3834	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
1159	1	1
1174	1	1
1190	1	1
1206	1	1
1222	1	1
1238	1	1
1254	1	1
1270	1	1
1286	1	1
1302	1	1
1318	1	1
1334	1	1
1350	1	1
1366	1	1
1382	1	1
1398	1	1
1404	1	1
1418	1	1
1806	1	1
1834	1	1
1862	1	1
1890	1	1
1918	1	1
1946	1	1
1987	1	1
2015	1	1
2043	1	1
2071	1	1
2112	1	1
2140	1	1
2181	1	1
2209	1	1
2237	1	1
2961	1	1
3079	1	1
3094	1	1
3110	1	1
3271	1	1
3272	1	1
3273	1	1
3274	1	1
3275	1	1
3276	1	1
3277	1	1
3278	1	1
3279	1	1
3280	1	1
3281	1	1
3282	1	1
3283	1	1
3284	1	1
3285	1	1
3286	1	1
3287	1	1
3288	1	1
3289	1	1
3290	1	1
3291	1	1
3292	1	1
3293	1	1
3294	1	1
3295	1	1
3296	1	1
3297	1	1
3298	1	1
3299	1	1
3300	1	1
3301	1	1
3302	1	1
3305	1	1
3309	1	1
3344	1	1
3346	1	1
3348	1	1
3350	1	1
3352	1	1
3354	1	1
3356	1	1
3358	1	1
3360	1	1
3361	1	1
3363	1	1
3365	1	1
3367	1	1
3369	1	1
3371	1	1
3373	1	1
3375	1	1
3377	1	1
3379	1	1
3381	1	1
3383	1	1
3385	1	1
3387	1	1
3389	1	1
3391	1	1
3392	1	1
3394	1	1
3396	1	1
3398	1	1
3400	1	1
3402	1	1
3404	1	1
3406	1	1
3408	1	1
3410	1	1
3412	1	1
3414	1	1
3416	1	1
3418	1	1
3420	1	1
3422	1	1
3423	1	1
3425	1	1
3426	1	1
3428	1	1
3430	1	1
3432	1	1
3434	1	1
3436	1	1
3438	1	1
3439	1	1
3440	1	1
3441	1	1
3443	1	1
3445	1	1
3447	1	1
3449	1	1
3451	1	1
3453	1	1
3454	1	1
3456	1	1
3458	1	1
3460	1	1
3462	1	1
3463	1	1
3465	1	1
3467	1	1
3468	1	1
3470	1	1
3472	1	1
3474	1	1
3475	1	1
3476	1	1
3477	1	1
3479	1	1
3481	1	1
3483	1	1
3484	1	1
3485	1	1
3487	1	1
3489	1	1
3490	1	1
3492	1	1
3494	1	1
3495	1	1
3497	1	1
3499	1	1
3500	1	1
3502	1	1
3504	1	1
3505	1	1
3507	1	1
3509	1	1
3510	1	1
3512	1	1
3514	1	1
3516	1	1
3517	1	1
3519	1	1
3521	1	1
3523	1	1
3525	1	1
3526	1	1
3527	1	1
3529	1	1
3530	1	1
3532	1	1
3533	1	1
3535	1	1
3537	1	1
3538	1	1
3541	1	1
3542	1	1
3544	1	1
3546	1	1
3547	1	1
3548	1	1
3550	1	1
3552	1	1
3553	1	1
3555	1	1
3557	1	1
3559	1	1
3563	1	1
3564	1	1
3565	1	1
3566	1	1
3567	1	1
3568	1	1
3569	1	1
3570	1	1
3571	1	1
3572	1	1
3573	1	1
3574	1	1
3575	1	1
3576	1	1
3577	1	1
3578	1	1
3579	1	1
3580	1	1
3581	1	1
3582	1	1
3583	1	1
3584	1	1
3585	1	1
3586	1	1
3587	1	1
3588	1	1
3589	1	1
3590	1	1
3591	1	1
3592	1	1
3593	1	1
3594	1	1
3599	1	1
3600	1	1
3602	1	1
3603	1	1
3604	1	1
3605	1	1
3606	1	1
3607	1	1
3608	1	1
3609	1	1
3610	1	1
3611	1	1
3612	1	1
3613	1	1
3614	1	1
3615	1	1
3616	1	1
3620	1	1
3621	1	1
3622	1	1
3623	1	1
3624	1	1
3625	1	1
3626	1	1
3627	1	1
3628	1	1
3629	1	1
3630	1	1
3631	1	1
3632	1	1
3633	1	1
3634	1	1
3638	1	1
3639	1	1
3640	1	1
3641	1	1
3642	1	1
3643	1	1
3644	1	1
3645	1	1
3646	1	1
3647	1	1
3648	1	1
3649	1	1
3650	1	1
3651	1	1
3652	1	1
3656	1	1
3660	1	1
3661	1	1
3662	1	1
3663	1	1
3664	1	1
3665	1	1
3669	1	1
3670	1	1
3671	1	1
3672	1	1
3673	1	1
3674	1	1
3675	1	1
3676	1	1
3677	1	1
3678	1	1
3679	1	1
3683	1	1
3687	1	1
3688	1	1
3689	1	1
3690	1	1
3691	1	1
3692	1	1
3696	1	1
3697	1	1
3698	1	1
3699	1	1
3703	1	1
3704	1	1
3708	1	1
3709	1	1
3710	1	1
3714	1	1
3715	1	1
3719	1	1
3720	1	1
3724	1	1
3725	1	1
3726	1	1
3730	1	1
3731	1	1
3735	1	1
3736	1	1
3740	1	1
3741	1	1
3745	1	1
3746	1	1
3750	1	1
3751	1	1
3755	1	1
3756	1	1
3760	1	1
3761	1	1
3762	1	1
3766	1	1
3767	1	1
3768	1	1
3769	1	1
3773	1	1
3774	1	1
3778	1	1
3782	1	1
3786	1	1
3787	1	1
3791	1	1
3795	1	1
3796	1	1
3800	1	1
3804	1	1
3805	1	1
3809	1	1
3810	1	1
3811	1	1
3825		unreachable
3833	1	1
3834	1	1

---

Cond Coverage for Module : i2c_reg_top

	Total	Covered	Percent
Conditions	337	333	98.81
Logical	337	333	98.81
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T129,T131,T132
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T116,T117,T118
1	0	Covered	T82,T130,T133

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T116,T117,T118
0	1	0	Covered	T82,T130,T133
1	0	0	Covered	T116,T117,T118

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T82,T130,T133
0	1	0	Covered	T114,T115,T129
1	0	0	Covered	T114,T115,T129

 LINE       3272
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3273
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3274
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T43,T26

 LINE       3275
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T43,T26

 LINE       3276
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3277
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3278
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3279
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3280
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3281
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3282
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3283
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T43,T26

 LINE       3284
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       3285
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T9,T43

 LINE       3286
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T43,T26

 LINE       3287
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3288
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3289
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3290
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3291
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3292
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3293
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       3294
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       3295
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       3296
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       3297
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_TIMEOUT_CTRL_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T43,T26

 LINE       3298
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_NACK_COUNT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T43,T26

 LINE       3299
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ACK_CTRL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T43

 LINE       3300
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQ_FIFO_NEXT_DATA_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T43,T26

 LINE       3301
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T43

 LINE       3302
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CONTROLLER_EVENTS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3305
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3305
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       3309
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T82,T114,T115

 LINE       3309
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b0111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
31 (addr_hit[30] & ((|(4'...	Covered	T5,T43,T26
30 (addr_hit[29] & ((|(4'...	Covered	T5,T43,T26
29 (addr_hit[28] & ((|(4'...	Covered	T5,T43,T26
28 (addr_hit[27] & ((|(4'...	Covered	T5,T43,T26
27 (addr_hit[26] & ((|(4'...	Covered	T5,T43,T26
26 (addr_hit[25] & ((|(4'...	Covered	T5,T43,T26
25 (addr_hit[24] & ((|(4'...	Covered	T5,T43,T26
24 (addr_hit[23] & ((|(4'...	Covered	T5,T43,T26
23 (addr_hit[22] & ((|(4'...	Covered	T1,T2,T5
22 (addr_hit[21] & ((|(4'...	Covered	T5,T43,T26
21 (addr_hit[20] & ((|(4'...	Covered	T5,T43,T26
20 (addr_hit[19] & ((|(4'...	Covered	T5,T43,T26
19 (addr_hit[18] & ((|(4'...	Covered	T5,T43,T26
18 (addr_hit[17] & ((|(4'...	Covered	T5,T43,T26
17 (addr_hit[16] & ((|(4'...	Covered	T5,T43,T26
16 (addr_hit[15] & ((|(4'...	Covered	T5,T43,T26
15 (addr_hit[14] & ((|(4'...	Covered	T5,T43,T26
14 (addr_hit[13] & ((|(4'...	Covered	T5,T9,T43
13 (addr_hit[12] & ((|(4'...	Covered	T1,T2,T5
12 (addr_hit[11] & ((|(4'...	Covered	T5,T43,T26
11 (addr_hit[10] & ((|(4'...	Covered	T5,T43,T26
10 (addr_hit[9] & ((|(4'b...	Covered	T5,T43,T26
9 (addr_hit[8] & ((|(4'b...	Covered	T5,T43,T26
8 (addr_hit[7] & ((|(4'b...	Covered	T5,T43,T26
7 (addr_hit[6] & ((|(4'b...	Covered	T3,T4,T5
6 (addr_hit[5] & ((|(4'b...	Covered	T1,T2,T3
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T43,T26
4 (addr_hit[3] & ((|(4'b...	Covered	T5,T43,T26
3 (addr_hit[2] & ((|(4'b...	Covered	T5,T43,T26
2 (addr_hit[1] & ((|(4'b...	Covered	T5,T43,T26
1 (addr_hit[0] & ((|(4'b...	Covered	T3,T4,T5

 LINE       3309
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       3309
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T43,T26
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T43,T26
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       3309
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       3309
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T43,T26
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T43,T26
1	1	Covered	T1,T2,T5

 LINE       3309
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T43
1	1	Covered	T5,T9,T43

 LINE       3309
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T26,T48
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       3309
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T43,T26
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T43,T26
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T43
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T43,T26
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T43
1	1	Covered	T5,T43,T26

 LINE       3309
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T43,T26

 LINE       3344
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T133,T131,T134
1	1	1	Covered	T1,T2,T3

 LINE       3361
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T114,T129,T131
1	1	1	Covered	T1,T2,T3

 LINE       3392
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T43,T26
1	1	0	Covered	T129,T131,T135
1	1	1	Covered	T49,T46,T35

 LINE       3423
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T43,T26
1	1	0	Covered	T132,T136,T137
1	1	1	Covered	T111,T112,T113

 LINE       3426
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T114,T130,T138
1	1	1	Covered	T1,T2,T3

 LINE       3439
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T139
1	1	1	Covered	T1,T2,T3

 LINE       3440
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T140,T141,T142
1	1	1	Covered	T3,T4,T8

 LINE       3441
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T114,T129,T132
1	1	1	Covered	T3,T4,T6

 LINE       3454
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T82,T114,T129
1	1	1	Covered	T1,T2,T3

 LINE       3463
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T114,T143,T144
1	1	1	Covered	T1,T2,T3

 LINE       3468
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T129,T131,T145
1	1	1	Covered	T1,T2,T3

 LINE       3475
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T43,T26
1	1	0	Covered	T130,T145,T142
1	1	1	Covered	T48,T49,T46

 LINE       3476
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T146,T140,T147
1	1	1	Covered	T1,T2,T5

 LINE       3477
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T9,T43
1	1	0	Covered	T114,T129,T131
1	1	1	Covered	T9,T44,T45

 LINE       3484
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T43,T26
1	1	0	Covered	T148,T142
1	1	1	Not Covered

 LINE       3485
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T129,T131,T132
1	1	1	Covered	T1,T2,T3

 LINE       3490
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T114,T130,T129
1	1	1	Covered	T1,T2,T3

 LINE       3495
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T114,T115,T149
1	1	1	Covered	T1,T2,T3

 LINE       3500
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T129,T131,T132
1	1	1	Covered	T1,T2,T3

 LINE       3505
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T131,T150,T137
1	1	1	Covered	T1,T2,T3

 LINE       3510
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T129,T131,T151
1	1	1	Covered	T1,T2,T3

 LINE       3517
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T114,T131,T132
1	1	1	Covered	T1,T2,T5

 LINE       3526
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T82,T145,T152
1	1	1	Covered	T1,T2,T5

 LINE       3527
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T114,T129,T131
1	1	1	Covered	T1,T2,T7

 LINE       3530
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T129,T131,T135
1	1	1	Covered	T1,T2,T5

 LINE       3533
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T43,T26
1	1	0	Covered	T114,T131,T132
1	1	1	Covered	T80,T81,T82

 LINE       3538
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T43,T26
1	1	0	Covered	T148,T146,T153
1	1	1	Covered	T80,T81,T82

 LINE       3541
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T43
1	1	0	Not Covered
1	1	1	Covered	T80,T81,T82

 LINE       3542
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T43
1	1	0	Covered	T114,T131,T145
1	1	1	Covered	T1,T5,T11

 LINE       3547
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T43,T26
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       3548
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T5,T43
1	1	0	Covered	T114,T131,T151
1	1	1	Covered	T3,T68,T69

 LINE       3553
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T82,T129,T135
1	1	1	Covered	T3,T4,T5

---

Branch Coverage for Module : i2c_reg_top

	Line No.	Total	Covered	Percent
Branches		37	37	100.00
TERNARY	3305	2	2	100.00
IF	68	3	3	100.00
CASE	3600	32	32	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	3305	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T116,T117,T118
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3600	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	413918739	58775863	0	0
reAfterRv	413918739	58775700	0	0
rePulse	413918739	57869898	0	0
wePulse	413918739	905802	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	58775863	0	0
T1	965139	7387	0	0
T2	282173	2429	0	0
T3	23397	10786	0	0
T4	128547	62482	0	0
T5	294393	1019	0	0
T6	11564	990	0	0
T7	101417	1078	0	0
T8	85891	12287	0	0
T9	3033	43	0	0
T10	166813	75315	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	58775700	0	0
T1	965139	7387	0	0
T2	282173	2429	0	0
T3	23397	10786	0	0
T4	128547	62482	0	0
T5	294393	1019	0	0
T6	11564	990	0	0
T7	101417	1078	0	0
T8	85891	12287	0	0
T9	3033	43	0	0
T10	166813	75315	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	57869898	0	0
T1	965139	3240	0	0
T2	282173	1132	0	0
T3	23397	10700	0	0
T4	128547	61718	0	0
T5	294393	925	0	0
T6	11564	973	0	0
T7	101417	699	0	0
T8	85891	11817	0	0
T9	3033	20	0	0
T10	166813	74578	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	905802	0	0
T1	965139	4147	0	0
T2	282173	1297	0	0
T3	23397	86	0	0
T4	128547	764	0	0
T5	294393	94	0	0
T6	11564	17	0	0
T7	101417	379	0	0
T8	85891	470	0	0
T9	3033	23	0	0
T10	166813	737	0	0