Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	413918739	6129	0	0
ctrl_rd_A	413918739	2158	0	0
host_fifo_config_rd_A	413918739	5900	0	0
host_nack_handler_timeout_rd_A	413918739	1365	0	0
host_timeout_ctrl_rd_A	413918739	1046	0	0
intr_enable_rd_A	413918739	4909	0	0
ovrd_rd_A	413918739	2384	0	0
target_fifo_config_rd_A	413918739	1759	0	0
target_id_rd_A	413918739	1930	0	0
target_timeout_ctrl_rd_A	413918739	1440	0	0
timeout_ctrl_rd_A	413918739	1717	0	0
timing0_rd_A	413918739	1335	0	0
timing1_rd_A	413918739	1359	0	0
timing2_rd_A	413918739	1387	0	0
timing3_rd_A	413918739	1422	0	0
timing4_rd_A	413918739	1324	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	6129	0	0
T82	12305	1	0	0
T114	4803	192	0	0
T115	2441	19	0	0
T129	2502	230	0	0
T131	10188	291	0	0
T132	2278	61	0	0
T133	4947	1	0	0
T138	2669	13	0	0
T143	1616	4	0	0
T149	1501	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	2158	0	0
T81	2733	11	0	0
T131	10188	9	0	0
T150	8173	155	0	0
T154	1914	9	0	0
T157	12143	197	0	0
T160	1803	17	0	0
T169	2343	37	0	0
T175	6031	52	0	0
T176	6888	66	0	0
T177	2369	19	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	5900	0	0
T31	246797	0	0	0
T45	1007	0	0	0
T46	643399	167	0	0
T66	203620	0	0	0
T89	268492	0	0	0
T96	63354	0	0	0
T97	27045	0	0	0
T98	134854	0	0	0
T178	0	148	0	0
T179	0	228	0	0
T180	0	127	0	0
T181	0	135	0	0
T182	0	93	0	0
T183	0	70	0	0
T184	0	80	0	0
T185	0	69	0	0
T186	0	114	0	0
T187	41625	0	0	0
T188	7928	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1365	0	0
T81	2733	11	0	0
T131	10188	9	0	0
T150	8173	50	0	0
T154	1914	2	0	0
T157	12143	220	0	0
T160	1803	6	0	0
T169	2343	11	0	0
T175	6031	45	0	0
T176	6888	39	0	0
T177	2369	14	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1046	0	0
T81	2733	3	0	0
T131	10188	31	0	0
T150	8173	34	0	0
T154	1914	12	0	0
T157	12143	192	0	0
T160	1803	2	0	0
T169	2343	3	0	0
T175	6031	61	0	0
T176	6888	7	0	0
T177	2369	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	4909	0	0
T31	246797	0	0	0
T45	1007	0	0	0
T46	643399	57	0	0
T66	203620	0	0	0
T77	0	10	0	0
T81	0	13	0	0
T89	268492	0	0	0
T96	63354	0	0	0
T97	27045	0	0	0
T98	134854	0	0	0
T154	0	13	0	0
T187	41625	0	0	0
T188	7928	0	0	0
T189	0	45	0	0
T190	0	12	0	0
T191	0	8	0	0
T192	0	12	0	0
T193	0	27	0	0
T194	0	32	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	2384	0	0
T9	3033	63	0	0
T10	166813	0	0	0
T11	34146	0	0	0
T26	129559	0	0	0
T27	264328	0	0	0
T43	10215	0	0	0
T47	12717	0	0	0
T48	443087	0	0	0
T79	12199	0	0	0
T83	149555	0	0	0
T195	0	37	0	0
T196	0	50	0	0
T197	0	26	0	0
T198	0	65	0	0
T199	0	38	0	0
T200	0	21	0	0
T201	0	44	0	0
T202	0	59	0	0
T203	0	48	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1759	0	0
T81	2733	9	0	0
T131	10188	24	0	0
T150	8173	94	0	0
T154	1914	11	0	0
T157	12143	242	0	0
T160	1803	7	0	0
T169	2343	32	0	0
T175	6031	52	0	0
T176	6888	65	0	0
T177	2369	12	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1930	0	0
T81	2733	9	0	0
T131	10188	7	0	0
T150	8173	66	0	0
T154	1914	21	0	0
T157	12143	204	0	0
T160	1803	6	0	0
T169	2343	42	0	0
T175	6031	55	0	0
T176	6888	52	0	0
T177	2369	29	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1440	0	0
T81	2733	8	0	0
T131	10188	17	0	0
T150	8173	86	0	0
T154	1914	7	0	0
T157	12143	246	0	0
T169	2343	5	0	0
T175	6031	51	0	0
T176	6888	44	0	0
T177	2369	12	0	0
T204	12716	14	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1717	0	0
T81	2733	9	0	0
T131	10188	6	0	0
T150	8173	103	0	0
T154	1914	13	0	0
T157	12143	234	0	0
T160	1803	10	0	0
T169	2343	3	0	0
T175	6031	77	0	0
T176	6888	30	0	0
T177	2369	9	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1335	0	0
T81	2733	6	0	0
T131	10188	18	0	0
T150	8173	68	0	0
T154	1914	17	0	0
T157	12143	201	0	0
T160	1803	6	0	0
T169	2343	15	0	0
T175	6031	61	0	0
T176	6888	32	0	0
T177	2369	7	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1359	0	0
T81	2733	14	0	0
T131	10188	15	0	0
T150	8173	58	0	0
T154	1914	15	0	0
T157	12143	203	0	0
T169	2343	10	0	0
T175	6031	55	0	0
T176	6888	31	0	0
T177	2369	3	0	0
T204	12716	12	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1387	0	0
T81	2733	2	0	0
T131	10188	10	0	0
T150	8173	58	0	0
T154	1914	8	0	0
T157	12143	230	0	0
T160	1803	10	0	0
T169	2343	19	0	0
T175	6031	91	0	0
T176	6888	30	0	0
T177	2369	18	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1422	0	0
T81	2733	11	0	0
T131	10188	31	0	0
T150	8173	59	0	0
T154	1914	13	0	0
T157	12143	221	0	0
T169	2343	8	0	0
T175	6031	87	0	0
T176	6888	20	0	0
T177	2369	4	0	0
T204	12716	19	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413918739	1324	0	0
T81	2733	1	0	0
T131	10188	9	0	0
T150	8173	77	0	0
T154	1914	7	0	0
T157	12143	200	0	0
T160	1803	7	0	0
T169	2343	18	0	0
T175	6031	77	0	0
T176	6888	23	0	0
T177	2369	7	0	0