Unified Coverage Report :: Module :: i2c_target_fsm

Module : i2c_target_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.31	87.31	76.58		81.11	76.54	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_target_fsm	84.31	87.31	76.58		81.11	76.54	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_target_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.31	87.31	76.58		81.11	76.54	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.31	87.31	76.58		81.11	76.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.03	97.30	71.15			91.67	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_target_fsm

	Line No.	Total	Covered	Percent
TOTAL		331	289	87.31
ALWAYS	123	8	7	87.50
ALWAYS	137	3	3	100.00
ALWAYS	147	5	5	100.00
ALWAYS	158	5	5	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	175	3	3	100.00
ALWAYS	184	3	3	100.00
ALWAYS	193	7	7	100.00
CONT_ASSIGN	205	1	1	100.00
ALWAYS	209	9	9	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
ALWAYS	232	7	7	100.00
ALWAYS	243	5	5	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	295	4	4	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
ALWAYS	324	126	106	84.13
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	621	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
ALWAYS	639	117	96	82.05
CONT_ASSIGN	971	1	1	100.00
ALWAYS	975	3	3	100.00
ALWAYS	984	3	3	100.00
CONT_ASSIGN	991	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	995	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	0	1
131	1	1
132	1	1
			MISSING_ELSE
137	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
150	1	1
152	1	1
158	1	1
159	1	1
160	1	1
162	1	1
164	1	1
168	1	1
169	1	1
170	1	1
171	1	1
175	1	1
176	1	1
178	1	1
184	1	1
185	1	1
187	1	1
193	1	1
194	1	1
195	1	1
196	1	1
198	1	1
199	1	1
200	1	1
205	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
216	2	2
217	1	1
219	1	1
224	1	1
226	1	1
228	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	2	2
			MISSING_ELSE
			MISSING_ELSE
243	1	1
244	1	1
245	1	1
246	2	2
			MISSING_ELSE
			MISSING_ELSE
260	1	1
263	1	1
264	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
312	1	1
316	1	1
320	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
341	1	1
346	1	1
347	1	1
348	1	1
349	1	1
350	1	1
351	1	1
360	1	1
361	1	1
362	1	1
366	1	1
367	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
			MISSING_ELSE
378	1	1
380	1	1
383	0	1
			MISSING_ELSE
388	1	1
389	1	1
393	1	1
394	1	1
398	1	1
399	1	1
402	1	1
403	1	1
407	1	1
409	1	1
			MISSING_ELSE
412	1	1
413	1	1
415	1	1
			==> MISSING_ELSE
421	1	1
425	1	1
426	1	1
430	1	1
433	1	1
437	1	1
440	1	1
444	1	1
447	1	1
448	1	1
450	1	1
			MISSING_ELSE
455	1	1
456	1	1
457	1	1
461	1	1
465	1	1
466	1	1
469	0	1
			MISSING_ELSE
474	1	1
475	1	1
479	1	1
480	1	1
484	1	1
485	1	1
487	1	1
488	1	1
489	1	1
490	1	1
			==> MISSING_ELSE
496	0	1
497	0	1
498	0	1
500	0	1
501	0	1
505	0	1
506	0	1
			==> MISSING_ELSE
512	0	1
513	0	1
514	0	1
519	1	1
520	1	1
521	1	1
523	1	1
524	0	1
528	0	1
529	0	1
530	1	1
531	1	1
532	1	1
533	1	1
535	1	1
			MISSING_ELSE
541	1	1
542	1	1
543	1	1
545	1	1
549	0	1
			MISSING_ELSE
554	1	1
555	1	1
556	1	1
560	1	1
561	1	1
562	1	1
563	1	1
566	1	1
567	0	1
568	0	1
569	0	1
			MISSING_ELSE
575	1	1
576	1	1
577	1	1
598	1	1
599	1	1
604	1	1
605	1	1
606	0	1
608	1	1
610	1	1
611	1	1
612	1	1
			MISSING_ELSE
616	1	1
617	1	1
621	1	1
630	1	1
635	1	1
639	1	1
640	1	1
641	1	1
642	1	1
643	1	1
645	1	1
657	1	1
658	1	1
659	1	1
			MISSING_ELSE
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
674	1	1
			MISSING_ELSE
680	1	1
682	0	1
683	1	1
684	1	1
686	1	1
688	0	1
695	0	1
696	0	1
699	0	1
703	0	1
			==> MISSING_ELSE
710	2	2
			MISSING_ELSE
714	1	1
715	1	1
716	1	1
717	1	1
			MISSING_ELSE
722	1	1
728	1	1
734	0	1
735	1	1
741	1	1
742	1	1
744	1	1
747	1	1
			==> MISSING_ELSE
753	1	1
754	1	1
756	1	1
761	2	2
			MISSING_ELSE
765	1	1
766	1	1
767	1	1
768	1	1
			MISSING_ELSE
773	1	1
774	1	1
775	1	1
777	1	1
778	1	1
779	1	1
			==> MISSING_ELSE
785	1	1
786	1	1
			MISSING_ELSE
792	1	1
794	1	1
795	1	1
798	1	1
			MISSING_ELSE
806	1	1
810	1	1
811	1	1
812	1	1
813	1	1
			MISSING_ELSE
818	1	1
820	0	1
821	1	1
822	1	1
823	0	1
824	1	1
828	1	1
830	1	1
			==> MISSING_ELSE
836	2	2
			MISSING_ELSE
840	1	1
841	1	1
842	1	1
843	1	1
			MISSING_ELSE
848	1	1
849	1	1
			==> MISSING_ELSE
857	0	1
858	0	1
859	0	1
860	0	1
861	0	1
862	0	1
			==> MISSING_ELSE
868	0	1
869	0	1
			==> MISSING_ELSE
877	1	1
878	0	1
879	1	1
885	1	1
			MISSING_ELSE
891	1	1
892	1	1
893	0	1
894	1	1
901	1	1
902	1	1
903	1	1
906	1	1
			MISSING_ELSE
911	1	1
912	1	1
			MISSING_ELSE
923	1	1
924	0	1
925	1	1
926	1	1
927	1	1
928	1	1
			MISSING_ELSE
934	1	1
935	1	1
			MISSING_ELSE
951	1	1
960	0	1
961	1	1
962	1	1
963	1	1
964	1	1
			MISSING_ELSE
971	1	1
975	1	1
976	1	1
978	1	1
984	1	1
985	1	1
987	1	1
991	1	1
992	1	1
995	1	1

---

Cond Coverage for Module : i2c_target_fsm

	Total	Covered	Percent
Conditions	111	85	76.58
Logical	111	85	76.58
Non-Logical	0	0
Event	0	0

 LINE       160
 EXPRESSION (auto_ack_load_i && ack_ctrl_stretching)
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Not Covered
1	1	Covered	T1,T5,T11

 LINE       168
 EXPRESSION (((!ack_ctrl_mode_i)) || (auto_ack_cnt_q > '0))
             ----------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T11
0	1	Covered	T1,T5,T11
1	0	Covered	T1,T2,T3

 LINE       205
 EXPRESSION (bit_idx == 4'd8)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       216
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5

 LINE       224
 EXPRESSION (((input_byte[7:1] & target_mask0_i) == target_address0_i) && (target_mask0_i != '0))
             ----------------------------1----------------------------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       224
 SUB-EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
                ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (target_mask0_i != '0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       226
 EXPRESSION (((input_byte[7:1] & target_mask1_i) == target_address1_i) && (target_mask1_i != '0))
             ----------------------------1----------------------------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       226
 SUB-EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
                ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       226
 SUB-EXPRESSION (target_mask1_i != '0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       228
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       236
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       297
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       316
 EXPRESSION (target_enable_i & xfer_for_us_q & rw_bit_q & stop_detect_i & ((!expect_stop)))
             -------1-------   ------2------   ----3---   ------4------   --------5-------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Not Covered
1	0	1	1	1	Covered	T12,T13,T14
1	1	0	1	1	Covered	T1,T2,T5
1	1	1	0	1	Covered	T1,T2,T7
1	1	1	1	0	Covered	T1,T2,T7
1	1	1	1	1	Covered	T12,T15,T14

 LINE       320
 EXPRESSION (((!nack_transaction_q)) && nack_transaction_d)
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       402
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       487
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       566
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T11
0	1	Not Covered
1	0	Not Covered

 LINE       566
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Not Covered
1	1	Not Covered

 LINE       598
 EXPRESSION (target_enable_i && stop_detect_i)
             -------1-------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       610
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       616
 EXPRESSION (((!acq_fifo_plenty_space)) || ((!can_auto_ack)))
             -------------1------------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T11
1	0	Covered	T16,T17,T18

 LINE       621
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       630
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       683
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       722
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       773
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T7

 LINE       821
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       848
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T5

 LINE       868
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       885
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Not Covered

 LINE       911
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T7

 LINE       923
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T11
0	1	Not Covered
1	0	Not Covered

 LINE       923
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Not Covered
1	1	Not Covered

 LINE       934
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T11
1	Covered	T1,T5,T11

 LINE       951
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Not Covered

 LINE       961
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       971
 EXPRESSION (target_enable_i && ((!target_idle)) && (stop_detect_i | start_detect_i))
             -------1-------    --------2-------    ----------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       971
 SUB-EXPRESSION (stop_detect_i | start_detect_i)
                 ------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : i2c_target_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	26	24	92.31	(Not included in score)
Transitions	90	73	81.11
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AcquireAckHold	841	Covered	T1,T2,T5
AcquireAckPulse	836	Covered	T1,T2,T5
AcquireAckSetup	830	Covered	T1,T2,T5
AcquireAckWait	811	Covered	T1,T2,T5
AcquireByte	747	Covered	T1,T2,T5
AcquireStart	962	Covered	T1,T2,T5
AddrAckHold	715	Covered	T1,T2,T5
AddrAckPulse	710	Covered	T1,T2,T5
AddrAckSetup	686	Covered	T1,T2,T5
AddrAckWait	668	Covered	T1,T2,T5
AddrRead	658	Covered	T1,T2,T5
Idle	960	Covered	T1,T2,T3
StretchAcqFull	828	Covered	T1,T5,T11
StretchAcqSetup	926	Covered	T1,T5,T11
StretchAddr	741	Covered	T16,T17,T18
StretchAddrAck	699	Not Covered
StretchAddrAckSetup	860	Not Covered
StretchTx	754	Covered	T1,T2,T7
StretchTxSetup	901	Covered	T1,T2,T7
TransmitAck	775	Covered	T1,T2,T7
TransmitAckPulse	786	Covered	T1,T2,T7
TransmitHold	766	Covered	T1,T2,T7
TransmitPulse	761	Covered	T1,T2,T7
TransmitSetup	756	Covered	T1,T2,T7
TransmitWait	744	Covered	T1,T2,T7
WaitForStop	674	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
AcquireAckHold->AcquireByte	849	Covered	T1,T2,T5
AcquireAckHold->AcquireStart	962	Covered	T12,T14
AcquireAckHold->Idle	960	Covered	T12,T14
AcquireAckPulse->AcquireAckHold	841	Covered	T1,T2,T5
AcquireAckPulse->AcquireStart	962	Covered	T12,T14
AcquireAckPulse->Idle	960	Covered	T12,T14
AcquireAckSetup->AcquireAckPulse	836	Covered	T1,T2,T5
AcquireAckSetup->AcquireStart	962	Covered	T12,T14
AcquireAckSetup->Idle	960	Covered	T12,T14
AcquireAckWait->AcquireAckSetup	830	Covered	T1,T2,T5
AcquireAckWait->AcquireStart	962	Covered	T12,T14
AcquireAckWait->Idle	960	Covered	T12,T14
AcquireAckWait->StretchAcqFull	828	Covered	T1,T5,T11
AcquireAckWait->WaitForStop	820	Not Covered
AcquireByte->AcquireAckWait	811	Covered	T1,T2,T5
AcquireByte->AcquireStart	962	Covered	T1,T2,T5
AcquireByte->Idle	960	Covered	T1,T2,T5
AcquireStart->AddrRead	658	Covered	T1,T2,T5
AcquireStart->Idle	960	Covered	T12,T14
AddrAckHold->AcquireByte	747	Covered	T1,T2,T5
AddrAckHold->AcquireStart	962	Covered	T12,T14
AddrAckHold->Idle	960	Covered	T12,T14
AddrAckHold->StretchAddr	741	Covered	T16,T17,T18
AddrAckHold->TransmitWait	744	Covered	T1,T2,T7
AddrAckHold->WaitForStop	734	Not Covered
AddrAckPulse->AcquireStart	962	Covered	T12,T14
AddrAckPulse->AddrAckHold	715	Covered	T1,T2,T5
AddrAckPulse->Idle	960	Covered	T12,T14
AddrAckSetup->AcquireStart	962	Covered	T12,T14
AddrAckSetup->AddrAckPulse	710	Covered	T1,T2,T5
AddrAckSetup->Idle	960	Covered	T12,T14
AddrAckWait->AcquireStart	962	Covered	T12,T14
AddrAckWait->AddrAckSetup	686	Covered	T1,T2,T5
AddrAckWait->Idle	960	Covered	T12,T14
AddrAckWait->StretchAddrAck	699	Not Covered
AddrAckWait->WaitForStop	682	Not Covered
AddrRead->AcquireStart	962	Covered	T12,T19,T20
AddrRead->AddrAckWait	668	Covered	T1,T2,T5
AddrRead->Idle	960	Covered	T12,T21,T22
AddrRead->WaitForStop	674	Covered	T23,T24,T25
Idle->AcquireStart	962	Covered	T1,T2,T5
StretchAcqFull->AcquireStart	962	Covered	T12,T14
StretchAcqFull->Idle	960	Covered	T12,T14
StretchAcqFull->StretchAcqSetup	926	Covered	T1,T5,T11
StretchAcqFull->WaitForStop	924	Not Covered
StretchAcqSetup->AcquireAckSetup	935	Covered	T1,T5,T11
StretchAcqSetup->AcquireStart	962	Not Covered
StretchAcqSetup->Idle	960	Not Covered
StretchAddr->AcquireByte	885	Covered	T16,T17,T18
StretchAddr->AcquireStart	962	Covered	T12,T14
StretchAddr->Idle	960	Covered	T12,T14
StretchAddr->StretchTx	885	Not Covered
StretchAddr->WaitForStop	878	Not Covered
StretchAddrAck->AcquireStart	962	Not Covered
StretchAddrAck->Idle	960	Not Covered
StretchAddrAck->StretchAddrAckSetup	860	Not Covered
StretchAddrAck->WaitForStop	858	Not Covered
StretchAddrAckSetup->AcquireStart	962	Not Covered
StretchAddrAckSetup->AddrAckSetup	869	Not Covered
StretchAddrAckSetup->Idle	960	Not Covered
StretchTx->AcquireStart	962	Covered	T12,T14
StretchTx->Idle	960	Covered	T12,T14
StretchTx->StretchTxSetup	901	Covered	T1,T2,T7
StretchTx->WaitForStop	893	Not Covered
StretchTxSetup->AcquireStart	962	Covered	T12,T14
StretchTxSetup->Idle	960	Covered	T12,T14
StretchTxSetup->TransmitSetup	912	Covered	T1,T2,T7
TransmitAck->AcquireStart	962	Covered	T12,T14
TransmitAck->Idle	960	Covered	T12,T14
TransmitAck->TransmitAckPulse	786	Covered	T1,T2,T7
TransmitAckPulse->AcquireStart	962	Covered	T12,T14
TransmitAckPulse->Idle	960	Covered	T12,T14
TransmitAckPulse->TransmitWait	795	Covered	T1,T2,T7
TransmitAckPulse->WaitForStop	798	Covered	T1,T2,T7
TransmitHold->AcquireStart	962	Covered	T12,T14
TransmitHold->Idle	960	Covered	T12,T14
TransmitHold->TransmitAck	775	Covered	T1,T2,T7
TransmitHold->TransmitSetup	779	Covered	T1,T2,T7
TransmitPulse->AcquireStart	962	Covered	T12,T15,T14
TransmitPulse->Idle	960	Covered	T12,T15,T14
TransmitPulse->TransmitHold	766	Covered	T1,T2,T7
TransmitSetup->AcquireStart	962	Covered	T12,T14
TransmitSetup->Idle	960	Covered	T12,T14
TransmitSetup->TransmitPulse	761	Covered	T1,T2,T7
TransmitWait->AcquireStart	962	Covered	T12,T14
TransmitWait->Idle	960	Covered	T12,T14
TransmitWait->StretchTx	754	Covered	T1,T2,T7
TransmitWait->TransmitSetup	756	Covered	T1,T2,T7
WaitForStop->AcquireStart	962	Covered	T1,T2,T7
WaitForStop->Idle	960	Covered	T1,T2,T7

---

Branch Coverage for Module : i2c_target_fsm

	Line No.	Total	Covered	Percent
Branches		162	124	76.54
IF	124	6	4	66.67
IF	137	2	2	100.00
IF	147	3	3	100.00
IF	158	3	3	100.00
IF	175	2	2	100.00
IF	184	2	2	100.00
IF	193	2	2	100.00
IF	209	5	5	100.00
IF	232	5	5	100.00
IF	243	4	4	100.00
IF	295	3	3	100.00
CASE	341	44	32	72.73
IF	598	4	3	75.00
CASE	645	69	47	68.12
IF	951	4	3	75.00
IF	975	2	2	100.00
IF	984	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	124	if (load_tcount)
-2-:	125	case (tcount_sel)
-3-:	131	if (target_enable_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupData	-	Covered	T1,T2,T5
1	tHoldData	-	Covered	T1,T2,T5
1	tNoDelay	-	Not Covered
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	147	if ((!rst_ni))
-2-:	149	if (actively_stretching)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	158	if ((!rst_ni))
-2-:	160	if ((auto_ack_load_i && ack_ctrl_stretching))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	175	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	184	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	if ((!rst_ni))
-2-:	211	if (start_detect_i)
-3-:	213	if ((scl_i_q && (!scl_i)))
-4-:	216	if ((input_byte_clr || bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (input_byte_clr)
-3-:	236	if (((!scl_i_q) && scl_i))
-4-:	237	if ((!bit_ack))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T5
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if ((!rst_ni))
-2-:	245	if (((!scl_i_q) && scl_i))
-3-:	246	if (bit_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	295	if ((!rst_ni))
-2-:	297	if ((bit_ack && address_match))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	case (state_q)
-2-:	369	if (bit_ack)
-3-:	370	if (address_match)
-4-:	380	if (scl_i)
-5-:	402	if ((tcount_q == 16'b1))
-6-:	403	if (nack_transaction_q)
-7-:	407	if ((!stretch_addr))
-8-:	412	if (restart_det_q)
-9-:	448	if ((!scl_i))
-10-:	466	if (scl_i)
-11-:	487	if ((tcount_q == 16'b1))
-12-:	500	if (nack_timeout)
-13-:	523	if (nack_timeout)
-14-:	530	if ((!stretch_addr))
-15-:	532	if (restart_det_q)
-16-:	545	if (nack_timeout)
-17-:	566	if ((nack_timeout || (sw_nack_i && (!can_auto_ack))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
Idle	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25
AddrRead	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckWait	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckHold	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18
AddrAckHold	-	-	-	1	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	1	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitAckPulse	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitAckPulse	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	Covered	T16,T17,T18
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	Covered	T16,T17,T18
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T16,T17,T18
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T7
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T11
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	598	if ((target_enable_i && stop_detect_i))
-2-:	605	if (nack_transaction_q)
-3-:	610	if ((target_enable_i && start_detect_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	-	Covered	T1,T2,T5
0	-	1	Covered	T1,T2,T5
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	645	case (state_q)
-2-:	657	if ((!scl_i))
-3-:	666	if (bit_ack)
-4-:	667	if (address_match)
-5-:	680	if (scl_i)
-6-:	683	if ((tcount_q == 16'b1))
-7-:	684	if ((!nack_addr_after_timeout_i))
-8-:	688	if (nack_transaction_q)
-9-:	696	if (stretch_addr)
-10-:	710	if (scl_i)
-11-:	714	if ((!scl_i))
-12-:	722	if ((tcount_q == 16'b1))
-13-:	728	if (nack_transaction_q)
-14-:	735	if (stretch_addr)
-15-:	742	if (rw_bit_q)
-16-:	753	if (stretch_tx)
-17-:	761	if (scl_i)
-18-:	765	if ((!scl_i))
-19-:	773	if ((tcount_q == 16'b1))
-20-:	774	if (bit_ack)
-21-:	785	if (scl_i)
-22-:	792	if ((!scl_i))
-23-:	794	if (host_ack)
-24-:	810	if (bit_ack)
-25-:	818	if (scl_i)
-26-:	821	if ((tcount_q == 16'b1))
-27-:	822	if (nack_transaction_q)
-28-:	824	if (stretch_rx)
-29-:	836	if (scl_i)
-30-:	840	if ((!scl_i))
-31-:	848	if ((tcount_q == 16'b1))
-32-:	857	if (nack_timeout)
-33-:	859	if ((!stretch_addr))
-34-:	868	if ((tcount_q == 16'b1))
-35-:	877	if (nack_timeout)
-36-:	879	if ((!stretch_addr))
-37-:	885	(rw_bit_q) ? 
-38-:	892	if (nack_timeout)
-39-:	894	if ((!stretch_tx))
-40-:	911	if ((tcount_q == 16'b1))
-41-:	923	if ((nack_timeout || (sw_nack_i && (!can_auto_ack))))
-42-:	925	if ((~stretch_rx))
-43-:	934	if ((tcount_q == 16'b1))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	Status	Tests
Idle	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
AcquireStart	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireStart	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrRead	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25
AddrRead	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckWait	-	-	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckWait	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckSetup	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckSetup	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
AddrAckHold	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AddrAckHold	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
TransmitAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
WaitForStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T11
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
AcquireAckHold	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddrAckSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	-	-	-	-	-	-	Not Covered
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	-	-	Covered	T16,T17,T18
StretchAddr	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T16,T17,T18
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T7
StretchTx	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T7
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T7
StretchTxSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T7
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T11
StretchAcqFull	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T11
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T11
StretchAcqSetup	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	951	if (((!target_idle) && (!target_enable_i)))
-2-:	961	if ((target_enable_i && start_detect_i))
-3-:	963	if (stop_detect_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	975	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	984	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_target_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqDepthRdCheck_A	413288883	3915568	0	0
AcqFifoDeepEnough_A	413288883	413117231	0	0
SclOutputGlitch_A	413288883	56129	0	0

AcqDepthRdCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288883	3915568	0	0
T1	965139	67391	0	0
T2	282173	14277	0	0
T3	23397	0	0	0
T4	128547	0	0	0
T5	294393	0	0	0
T6	11564	0	0	0
T7	101417	2424	0	0
T8	85891	0	0	0
T9	3033	0	0	0
T10	166813	0	0	0
T11	0	62	0	0
T26	0	1433	0	0
T27	0	7552	0	0
T28	0	376	0	0
T29	0	170	0	0
T30	0	6459	0	0
T31	0	11458	0	0

AcqFifoDeepEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288883	413117231	0	0
T1	965139	965068	0	0
T2	282173	282084	0	0
T3	23397	23326	0	0
T4	128547	128390	0	0
T5	294393	294307	0	0
T6	11564	11481	0	0
T7	101417	101317	0	0
T8	85891	85816	0	0
T9	3033	2949	0	0
T10	166813	166650	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413288883	56129	0	0
T1	965139	362	0	0
T2	282173	79	0	0
T3	23397	0	0	0
T4	128547	0	0	0
T5	294393	41	0	0
T6	11564	0	0	0
T7	101417	30	0	0
T8	85891	0	0	0
T9	3033	0	0	0
T10	166813	0	0	0
T11	0	21	0	0
T26	0	54	0	0
T27	0	172	0	0
T28	0	98	0	0
T30	0	39	0	0
T31	0	114	0	0