SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.i2c_core.u_i2c_sync_scl | |||||||
tb.dut.i2c_core.u_i2c_sync_sda |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.03 | 97.30 | 71.15 | 91.67 | 100.00 | i2c_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
u_sync_2 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.03 | 97.30 | 71.15 | 91.67 | 100.00 | i2c_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
u_sync_2 | 100.00 | 100.00 | 100.00 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |