Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.03 97.30 71.15 91.67 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core 90.03 97.30 71.15 91.67 100.00



Module Instance : tb.dut.i2c_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.03 97.30 71.15 91.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.52 96.08 86.35 83.58 91.84 94.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.72 100.00 100.00 94.87 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
intr_hw_acq_overflow 100.00 100.00 100.00 100.00 100.00
intr_hw_acq_threshold 100.00 100.00 100.00 100.00 100.00
intr_hw_cmd_complete 100.00 100.00 100.00 100.00 100.00
intr_hw_controller_halt 100.00 100.00 100.00 100.00 100.00
intr_hw_fmt_threshold 100.00 100.00 100.00 100.00 100.00
intr_hw_host_timeout 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_overflow 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_threshold 100.00 100.00 100.00 100.00 100.00
intr_hw_scl_interference 97.92 100.00 91.67 100.00 100.00
intr_hw_sda_interference 100.00 100.00 100.00 100.00 100.00
intr_hw_sda_unstable 100.00 100.00 100.00 100.00 100.00
intr_hw_stretch_timeout 100.00 100.00 100.00 100.00 100.00
intr_hw_tx_stretch 100.00 100.00 100.00 100.00 100.00
intr_hw_tx_threshold 100.00 100.00 100.00 100.00 100.00
intr_hw_unexp_stop 100.00 100.00 100.00 100.00 100.00
u_fifos 94.64 99.86 86.59 98.65 93.48
u_i2c_bus_monitor 89.50 96.26 90.32 81.82 89.58
u_i2c_controller_fsm 92.94 94.79 86.67 90.91 92.35 100.00
u_i2c_sync_scl 100.00 100.00 100.00
u_i2c_sync_sda 100.00 100.00 100.00
u_i2c_target_fsm 84.31 87.31 76.58 81.11 76.54 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_core
Line No.TotalCoveredPercent
TOTAL11110897.30
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19011100.00
CONT_ASSIGN19111100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN23411100.00
ALWAYS23855100.00
ALWAYS25055100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN26211100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN27011100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN31411100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33511100.00
CONT_ASSIGN33711100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN341100.00
CONT_ASSIGN342100.00
CONT_ASSIGN343100.00
CONT_ASSIGN34411100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN77711100.00
CONT_ASSIGN77911100.00
CONT_ASSIGN78111100.00
CONT_ASSIGN78211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
196 1 1
197 1 1
198 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
209 1 1
213 1 1
214 1 1
216 1 1
218 1 1
219 1 1
221 1 1
222 1 1
223 1 1
225 1 1
229 1 1
231 1 1
232 1 1
233 1 1
234 1 1
238 1 1
239 1 1
240 1 1
243 1 1
244 1 1
250 1 1
251 1 1
252 1 1
254 1 1
255 1 1
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
264 1 1
265 1 1
266 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
274 1 1
275 1 1
276 1 1
277 1 1
278 1 1
279 1 1
282 1 1
283 1 1
284 1 1
285 1 1
287 1 1
289 1 1
290 1 1
291 1 1
294 1 1
296 1 1
298 1 1
300 1 1
302 1 1
303 1 1
308 1 1
314 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
321 1 1
322 1 1
323 1 1
324 1 1
325 1 1
326 1 1
335 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 0 1
342 0 1
343 0 1
344 1 1
345 1 1
346 1 1
390 1 1
395 1 1
397 1 1
400 1 1
401 1 1
406 1 1
777 1 1
779 1 1
781 1 1
782 1 1


Cond Coverage for Module : i2c_core
TotalCoveredPercent
Conditions1047471.15
Logical1047471.15
Non-Logical00
Event00

 LINE       213
 EXPRESSION (event_target_nack && (reg2hw.target_nack_count.q < 8'hff))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       218
 EXPRESSION (override ? reg2hw.ovrd.sclval : scl_out_fsm)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT52,T56,T53

 LINE       219
 EXPRESSION (override ? reg2hw.ovrd.sdaval : sda_out_fsm)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT52,T56,T53

 LINE       225
 EXPRESSION (event_controller_cmd_complete | event_target_cmd_complete)
             --------------1--------------   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T8,T9
10CoveredT2,T5,T6

 LINE       229
 EXPRESSION (target_enable & line_loopback)
             ------1------   ------2------
-1--2-StatusTests
01Not Covered
10CoveredT4,T8,T9
11Not Covered

 LINE       243
 EXPRESSION (scl_out_controller_fsm & scl_out_target_fsm)
             -----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T21
11CoveredT1,T2,T3

 LINE       244
 EXPRESSION (sda_out_controller_fsm & sda_out_target_fsm)
             -----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T9
11CoveredT1,T2,T3

 LINE       270
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode))
             ------------1-----------    -------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       270
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == StretchTimeoutMode)
                -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       272
 EXPRESSION (reg2hw.timeout_ctrl.en.q && (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode))
             ------------1-----------    -----------------------2----------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       272
 SUB-EXPRESSION (reg2hw.timeout_ctrl.mode.q == BusTimeoutMode)
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       279
 EXPRESSION (reg2hw.target_ack_ctrl.nack.qe & reg2hw.target_ack_ctrl.nack.q)
             ---------------1--------------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T11,T12
11Not Covered

 LINE       282
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT10,T35,T50
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       283
 EXPRESSION (reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe)
             ------------1------------   -------------2------------
-1--2-StatusTests
01CoveredT10,T35,T50
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       287
 EXPRESSION ((reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe) || (reg2hw.target_fifo_config.txrst_on_cond.q & target_sr_p_cond))
             ---------------------------1--------------------------    -------------------------------2------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       287
 SUB-EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT10,T47,T50
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       287
 SUB-EXPRESSION (reg2hw.target_fifo_config.txrst_on_cond.q & target_sr_p_cond)
                 --------------------1--------------------   --------2-------
-1--2-StatusTests
01CoveredT4,T8,T9
10Not Covered
11Not Covered

 LINE       289
 EXPRESSION (reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe)
             ------------1------------   -------------2------------
-1--2-StatusTests
01CoveredT10,T47,T35
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       302
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T6
11CoveredT47,T57,T58

 LINE       303
 EXPRESSION (acq_fifo_full || target_ack_ctrl_stretching)
             ------1------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T11,T12
10CoveredT18,T19,T20

 LINE       308
 EXPRESSION (reg2hw.fdata.fbyte.qe & reg2hw.fdata.start.qe & reg2hw.fdata.stop.qe & reg2hw.fdata.readb.qe & reg2hw.fdata.rcont.qe & reg2hw.fdata.nakok.qe)
             ----------1----------   ----------2----------   ----------3---------   ----------4----------   ----------5----------   ----------6----------
-1--2--3--4--5--6-StatusTests
011111Not Covered
101111Not Covered
110111Not Covered
111011Not Covered
111101Not Covered
111110Not Covered
111111CoveredT1,T2,T3

 LINE       321
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[7:0] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       322
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[8] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       323
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[9] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       324
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[10] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       325
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[11] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       326
 EXPRESSION (fmt_fifo_rvalid ? fmt_fifo_rdata[12] : '0)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       397
 EXPRESSION (target_enable & (acq_type == AcqData))
             ------1------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T9
11CoveredT4,T8,T9

 LINE       397
 SUB-EXPRESSION (acq_type == AcqData)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       400
 EXPRESSION (target_loopback ? (acq_fifo_rvalid & valid_target_lb_wr) : reg2hw.txdata.qe)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       400
 SUB-EXPRESSION (acq_fifo_rvalid & valid_target_lb_wr)
                 -------1-------   ---------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       401
 EXPRESSION (target_loopback ? acq_fifo_rdata[7:0] : reg2hw.txdata.q)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       406
 EXPRESSION ((reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) | (target_loopback & (tx_fifo_wready | (acq_type != AcqData))))
             --------------------------1-------------------------   ------------------------------2-----------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T8,T9

 LINE       406
 SUB-EXPRESSION (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re)
                 -----------1-----------   ------------2-----------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT4,T8,T9

 LINE       406
 SUB-EXPRESSION (target_loopback & (tx_fifo_wready | (acq_type != AcqData)))
                 -------1-------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       406
 SUB-EXPRESSION (tx_fifo_wready | (acq_type != AcqData))
                 -------1------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT9,T35,T59
10CoveredT1,T2,T3

 LINE       406
 SUB-EXPRESSION (acq_type != AcqData)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T8,T9

 LINE       781
 EXPRESSION (event_bus_active_timeout && ((!host_idle)))
             ------------1-----------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Module : i2c_core
Line No.TotalCoveredPercent
Branches 24 22 91.67
TERNARY 218 2 2 100.00
TERNARY 219 2 2 100.00
TERNARY 321 2 2 100.00
TERNARY 322 2 2 100.00
TERNARY 323 2 2 100.00
TERNARY 324 2 2 100.00
TERNARY 325 2 2 100.00
TERNARY 326 2 2 100.00
TERNARY 400 2 1 50.00
TERNARY 401 2 1 50.00
IF 238 2 2 100.00
IF 250 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 218 (override) ?

Branches:
-1-StatusTests
1 Covered T52,T56,T53
0 Covered T1,T2,T3


LineNo. Expression -1-: 219 (override) ?

Branches:
-1-StatusTests
1 Covered T52,T56,T53
0 Covered T1,T2,T3


LineNo. Expression -1-: 321 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 322 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 323 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 324 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 325 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 326 (fmt_fifo_rvalid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 400 (target_loopback) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 401 (target_loopback) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 238 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 250 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : i2c_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AcqFifoDepthValid_A 1307 1307 0 0
FifoDepthValid_A 1307 1307 0 0
SclInputGlitch_A 410395107 9591902 0 0


AcqFifoDepthValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1307 1307 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

FifoDepthValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1307 1307 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SclInputGlitch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410395107 9591902 0 0
T1 5286 8 0 0
T2 46660 1791 0 0
T3 11196 55 0 0
T4 78778 3300 0 0
T5 36886 1415 0 0
T6 75474 3784 0 0
T7 696815 5071 0 0
T8 100747 6855 0 0
T9 127089 6256 0 0
T10 15172 586 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%