Module Definition
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Module : i2c_target_fsm
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.31 87.31 76.58 81.11 76.54 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_i2c_target_fsm 84.31 87.31 76.58 81.11 76.54 100.00



Module Instance : tb.dut.i2c_core.u_i2c_target_fsm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.31 87.31 76.58 81.11 76.54 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.31 87.31 76.58 81.11 76.54 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.03 97.30 71.15 91.67 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_target_fsm
Line No.TotalCoveredPercent
TOTAL33128987.31
ALWAYS1238787.50
ALWAYS13733100.00
ALWAYS14755100.00
ALWAYS15855100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17111100.00
ALWAYS17533100.00
ALWAYS18433100.00
ALWAYS19377100.00
CONT_ASSIGN20511100.00
ALWAYS20999100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22611100.00
CONT_ASSIGN22811100.00
ALWAYS23277100.00
ALWAYS24355100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26411100.00
ALWAYS29544100.00
CONT_ASSIGN31211100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS32412610684.13
CONT_ASSIGN61611100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62111100.00
CONT_ASSIGN63011100.00
CONT_ASSIGN63511100.00
ALWAYS6391179682.05
CONT_ASSIGN97111100.00
ALWAYS97533100.00
ALWAYS98433100.00
CONT_ASSIGN99111100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN99511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
128 0 1
131 1 1
132 1 1
MISSING_ELSE
137 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
150 1 1
152 1 1
158 1 1
159 1 1
160 1 1
162 1 1
164 1 1
168 1 1
169 1 1
170 1 1
171 1 1
175 1 1
176 1 1
178 1 1
184 1 1
185 1 1
187 1 1
193 1 1
194 1 1
195 1 1
196 1 1
198 1 1
199 1 1
200 1 1
205 1 1
209 1 1
210 1 1
211 1 1
212 1 1
213 1 1
216 2 2
217 1 1
219 1 1
224 1 1
226 1 1
228 1 1
232 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 2 2
MISSING_ELSE
MISSING_ELSE
243 1 1
244 1 1
245 1 1
246 2 2
MISSING_ELSE
MISSING_ELSE
260 1 1
263 1 1
264 1 1
295 1 1
296 1 1
297 1 1
298 1 1
MISSING_ELSE
312 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
330 1 1
331 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
341 1 1
346 1 1
347 1 1
348 1 1
349 1 1
350 1 1
351 1 1
360 1 1
361 1 1
362 1 1
366 1 1
367 1 1
369 1 1
370 1 1
371 1 1
372 1 1
MISSING_ELSE
MISSING_ELSE
378 1 1
380 1 1
383 0 1
MISSING_ELSE
388 1 1
389 1 1
393 1 1
394 1 1
398 1 1
399 1 1
402 1 1
403 1 1
407 1 1
409 1 1
MISSING_ELSE
412 1 1
413 1 1
415 1 1
==> MISSING_ELSE
421 1 1
425 1 1
426 1 1
430 1 1
433 1 1
437 1 1
440 1 1
444 1 1
447 1 1
448 1 1
450 1 1
MISSING_ELSE
455 1 1
456 1 1
457 1 1
461 1 1
465 1 1
466 1 1
469 0 1
MISSING_ELSE
474 1 1
475 1 1
479 1 1
480 1 1
484 1 1
485 1 1
487 1 1
488 1 1
489 1 1
490 1 1
==> MISSING_ELSE
496 0 1
497 0 1
498 0 1
500 0 1
501 0 1
505 0 1
506 0 1
==> MISSING_ELSE
512 0 1
513 0 1
514 0 1
519 1 1
520 1 1
521 1 1
523 1 1
524 0 1
528 0 1
529 0 1
530 1 1
531 1 1
532 1 1
533 1 1
535 1 1
MISSING_ELSE
541 1 1
542 1 1
543 1 1
545 1 1
549 0 1
MISSING_ELSE
554 1 1
555 1 1
556 1 1
560 1 1
561 1 1
562 1 1
563 1 1
566 1 1
567 0 1
568 0 1
569 0 1
MISSING_ELSE
575 1 1
576 1 1
577 1 1
598 1 1
599 1 1
604 1 1
605 1 1
606 0 1
608 1 1
610 1 1
611 1 1
612 1 1
MISSING_ELSE
616 1 1
617 1 1
621 1 1
630 1 1
635 1 1
639 1 1
640 1 1
641 1 1
642 1 1
643 1 1
645 1 1
657 1 1
658 1 1
659 1 1
MISSING_ELSE
666 1 1
667 1 1
668 1 1
670 1 1
671 1 1
674 1 1
MISSING_ELSE
680 1 1
682 0 1
683 1 1
684 1 1
686 1 1
688 0 1
695 0 1
696 0 1
699 0 1
703 0 1
==> MISSING_ELSE
710 2 2
MISSING_ELSE
714 1 1
715 1 1
716 1 1
717 1 1
MISSING_ELSE
722 1 1
728 1 1
734 0 1
735 1 1
741 1 1
742 1 1
744 1 1
747 1 1
==> MISSING_ELSE
753 1 1
754 1 1
756 1 1
761 2 2
MISSING_ELSE
765 1 1
766 1 1
767 1 1
768 1 1
MISSING_ELSE
773 1 1
774 1 1
775 1 1
777 1 1
778 1 1
779 1 1
==> MISSING_ELSE
785 1 1
786 1 1
MISSING_ELSE
792 1 1
794 1 1
795 1 1
798 1 1
MISSING_ELSE
806 1 1
810 1 1
811 1 1
812 1 1
813 1 1
MISSING_ELSE
818 1 1
820 0 1
821 1 1
822 1 1
823 0 1
824 1 1
828 1 1
830 1 1
==> MISSING_ELSE
836 2 2
MISSING_ELSE
840 1 1
841 1 1
842 1 1
843 1 1
MISSING_ELSE
848 1 1
849 1 1
==> MISSING_ELSE
857 0 1
858 0 1
859 0 1
860 0 1
861 0 1
862 0 1
==> MISSING_ELSE
868 0 1
869 0 1
==> MISSING_ELSE
877 1 1
878 0 1
879 1 1
885 1 1
MISSING_ELSE
891 1 1
892 1 1
893 0 1
894 1 1
901 1 1
902 1 1
903 1 1
906 1 1
MISSING_ELSE
911 1 1
912 1 1
MISSING_ELSE
923 1 1
924 0 1
925 1 1
926 1 1
927 1 1
928 1 1
MISSING_ELSE
934 1 1
935 1 1
MISSING_ELSE
951 1 1
960 0 1
961 1 1
962 1 1
963 1 1
964 1 1
MISSING_ELSE
971 1 1
975 1 1
976 1 1
978 1 1
984 1 1
985 1 1
987 1 1
991 1 1
992 1 1
995 1 1


Cond Coverage for Module : i2c_target_fsm
TotalCoveredPercent
Conditions1118576.58
Logical1118576.58
Non-Logical00
Event00

 LINE       160
 EXPRESSION (auto_ack_load_i && ack_ctrl_stretching)
             -------1-------    ---------2---------
-1--2-StatusTests
01CoveredT8,T11,T12
10Not Covered
11CoveredT8,T11,T12

 LINE       168
 EXPRESSION (((!ack_ctrl_mode_i)) || (auto_ack_cnt_q > '0))
             ----------1---------    ----------2----------
-1--2-StatusTests
00CoveredT8,T11,T12
01CoveredT8,T11,T12
10CoveredT1,T2,T3

 LINE       205
 EXPRESSION (bit_idx == 4'd8)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       213
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       216
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT4,T8,T9

 LINE       224
 EXPRESSION (((input_byte[7:1] & target_mask0_i) == target_address0_i) && (target_mask0_i != '0))
             ----------------------------1----------------------------    -----------2----------
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT1,T2,T3
11CoveredT4,T8,T9

 LINE       224
 SUB-EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
                ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       224
 SUB-EXPRESSION (target_mask0_i != '0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T8,T9

 LINE       226
 EXPRESSION (((input_byte[7:1] & target_mask1_i) == target_address1_i) && (target_mask1_i != '0))
             ----------------------------1----------------------------    -----------2----------
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT1,T2,T3
11CoveredT4,T8,T9

 LINE       226
 SUB-EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
                ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       226
 SUB-EXPRESSION (target_mask1_i != '0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T8,T9

 LINE       228
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T8,T9
10CoveredT4,T8,T9

 LINE       236
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       245
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       297
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT2,T3,T4
11CoveredT4,T8,T9

 LINE       316
 EXPRESSION (target_enable_i & xfer_for_us_q & rw_bit_q & stop_detect_i & ((!expect_stop)))
             -------1-------   ------2------   ----3---   ------4------   --------5-------
-1--2--3--4--5-StatusTests
01111Not Covered
10111CoveredT13,T14,T15
11011CoveredT4,T8,T9
11101CoveredT4,T8,T9
11110CoveredT4,T8,T9
11111CoveredT4,T16,T17

 LINE       320
 EXPRESSION (((!nack_transaction_q)) && nack_transaction_d)
             -----------1-----------    ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       402
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T8,T9

 LINE       487
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T8,T9

 LINE       566
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------
-1--2-StatusTests
00CoveredT8,T11,T12
01Not Covered
10Not Covered

 LINE       566
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------
-1--2-StatusTests
01CoveredT8,T11,T12
10Not Covered
11Not Covered

 LINE       598
 EXPRESSION (target_enable_i && stop_detect_i)
             -------1-------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T9
11CoveredT4,T8,T9

 LINE       610
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T9
11CoveredT4,T8,T9

 LINE       616
 EXPRESSION (((!acq_fifo_plenty_space)) || ((!can_auto_ack)))
             -------------1------------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T11,T12
10CoveredT18,T19,T20

 LINE       621
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       630
 EXPRESSION (((~tx_fifo_rvalid_i)) | (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------   --------------2--------------
-1--2-StatusTests
00CoveredT4,T8,T9
01CoveredT4,T8,T9
10CoveredT1,T2,T3

 LINE       683
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T8,T9

 LINE       722
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T8,T9

 LINE       773
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T8,T9

 LINE       821
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T8,T9

 LINE       848
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T8,T9

 LINE       868
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       885
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---
-1-StatusTests
0CoveredT18,T19,T20
1Not Covered

 LINE       911
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T8,T21
1CoveredT4,T8,T21

 LINE       923
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------
-1--2-StatusTests
00CoveredT8,T11,T12
01Not Covered
10Not Covered

 LINE       923
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------
-1--2-StatusTests
01CoveredT8,T11,T12
10Not Covered
11Not Covered

 LINE       934
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT8,T11,T12
1CoveredT8,T11,T12

 LINE       951
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T9
11Not Covered

 LINE       961
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T8,T9
11CoveredT4,T8,T9

 LINE       971
 EXPRESSION (target_enable_i && ((!target_idle)) && (stop_detect_i | start_detect_i))
             -------1-------    --------2-------    ----------------3---------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T8,T9
110CoveredT4,T8,T9
111CoveredT4,T8,T9

 LINE       971
 SUB-EXPRESSION (stop_detect_i | start_detect_i)
                 ------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

FSM Coverage for Module : i2c_target_fsm
Summary for FSM :: state_q
TotalCoveredPercent
States 26 24 92.31 (Not included in score)
Transitions 90 73 81.11
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AcquireAckHold 841 Covered T4,T8,T9
AcquireAckPulse 836 Covered T4,T8,T9
AcquireAckSetup 830 Covered T4,T8,T9
AcquireAckWait 811 Covered T4,T8,T9
AcquireByte 747 Covered T4,T8,T9
AcquireStart 962 Covered T4,T8,T9
AddrAckHold 715 Covered T4,T8,T9
AddrAckPulse 710 Covered T4,T8,T9
AddrAckSetup 686 Covered T4,T8,T9
AddrAckWait 668 Covered T4,T8,T9
AddrRead 658 Covered T4,T8,T9
Idle 960 Covered T1,T2,T3
StretchAcqFull 828 Covered T8,T11,T12
StretchAcqSetup 926 Covered T8,T11,T12
StretchAddr 741 Covered T18,T19,T20
StretchAddrAck 699 Not Covered
StretchAddrAckSetup 860 Not Covered
StretchTx 754 Covered T4,T8,T21
StretchTxSetup 901 Covered T4,T8,T21
TransmitAck 775 Covered T4,T8,T9
TransmitAckPulse 786 Covered T4,T8,T9
TransmitHold 766 Covered T4,T8,T9
TransmitPulse 761 Covered T4,T8,T9
TransmitSetup 756 Covered T4,T8,T9
TransmitWait 744 Covered T4,T8,T9
WaitForStop 674 Covered T4,T8,T9


transitionsLine No.CoveredTests
AcquireAckHold->AcquireByte 849 Covered T4,T8,T9
AcquireAckHold->AcquireStart 962 Covered T22,T23
AcquireAckHold->Idle 960 Covered T22,T23
AcquireAckPulse->AcquireAckHold 841 Covered T4,T8,T9
AcquireAckPulse->AcquireStart 962 Covered T22,T23
AcquireAckPulse->Idle 960 Covered T22,T23
AcquireAckSetup->AcquireAckPulse 836 Covered T4,T8,T9
AcquireAckSetup->AcquireStart 962 Covered T22,T23
AcquireAckSetup->Idle 960 Covered T22,T23
AcquireAckWait->AcquireAckSetup 830 Covered T4,T8,T9
AcquireAckWait->AcquireStart 962 Covered T22,T23
AcquireAckWait->Idle 960 Covered T22,T23
AcquireAckWait->StretchAcqFull 828 Covered T8,T11,T12
AcquireAckWait->WaitForStop 820 Not Covered
AcquireByte->AcquireAckWait 811 Covered T4,T8,T9
AcquireByte->AcquireStart 962 Covered T4,T8,T9
AcquireByte->Idle 960 Covered T4,T8,T9
AcquireStart->AddrRead 658 Covered T4,T8,T9
AcquireStart->Idle 960 Covered T22,T23
AddrAckHold->AcquireByte 747 Covered T4,T8,T9
AddrAckHold->AcquireStart 962 Covered T22,T23
AddrAckHold->Idle 960 Covered T22,T23
AddrAckHold->StretchAddr 741 Covered T18,T19,T20
AddrAckHold->TransmitWait 744 Covered T4,T8,T9
AddrAckHold->WaitForStop 734 Not Covered
AddrAckPulse->AcquireStart 962 Covered T22,T23
AddrAckPulse->AddrAckHold 715 Covered T4,T8,T9
AddrAckPulse->Idle 960 Covered T22,T23
AddrAckSetup->AcquireStart 962 Covered T22,T23
AddrAckSetup->AddrAckPulse 710 Covered T4,T8,T9
AddrAckSetup->Idle 960 Covered T22,T23
AddrAckWait->AcquireStart 962 Covered T22,T23
AddrAckWait->AddrAckSetup 686 Covered T4,T8,T9
AddrAckWait->Idle 960 Covered T22,T23
AddrAckWait->StretchAddrAck 699 Not Covered
AddrAckWait->WaitForStop 682 Not Covered
AddrRead->AcquireStart 962 Covered T24,T25,T26
AddrRead->AddrAckWait 668 Covered T4,T8,T9
AddrRead->Idle 960 Covered T27,T28,T29
AddrRead->WaitForStop 674 Covered T30,T31,T32
Idle->AcquireStart 962 Covered T4,T8,T9
StretchAcqFull->AcquireStart 962 Covered T22,T23
StretchAcqFull->Idle 960 Covered T22,T23
StretchAcqFull->StretchAcqSetup 926 Covered T8,T11,T12
StretchAcqFull->WaitForStop 924 Not Covered
StretchAcqSetup->AcquireAckSetup 935 Covered T8,T11,T12
StretchAcqSetup->AcquireStart 962 Not Covered
StretchAcqSetup->Idle 960 Not Covered
StretchAddr->AcquireByte 885 Covered T18,T19,T20
StretchAddr->AcquireStart 962 Covered T22,T23
StretchAddr->Idle 960 Covered T22,T23
StretchAddr->StretchTx 885 Not Covered
StretchAddr->WaitForStop 878 Not Covered
StretchAddrAck->AcquireStart 962 Not Covered
StretchAddrAck->Idle 960 Not Covered
StretchAddrAck->StretchAddrAckSetup 860 Not Covered
StretchAddrAck->WaitForStop 858 Not Covered
StretchAddrAckSetup->AcquireStart 962 Not Covered
StretchAddrAckSetup->AddrAckSetup 869 Not Covered
StretchAddrAckSetup->Idle 960 Not Covered
StretchTx->AcquireStart 962 Covered T22,T23
StretchTx->Idle 960 Covered T22,T23
StretchTx->StretchTxSetup 901 Covered T4,T8,T21
StretchTx->WaitForStop 893 Not Covered
StretchTxSetup->AcquireStart 962 Covered T22,T23
StretchTxSetup->Idle 960 Covered T22,T23
StretchTxSetup->TransmitSetup 912 Covered T4,T8,T21
TransmitAck->AcquireStart 962 Covered T22,T23
TransmitAck->Idle 960 Covered T22,T23
TransmitAck->TransmitAckPulse 786 Covered T4,T8,T9
TransmitAckPulse->AcquireStart 962 Covered T22,T23
TransmitAckPulse->Idle 960 Covered T22,T23
TransmitAckPulse->TransmitWait 795 Covered T4,T8,T9
TransmitAckPulse->WaitForStop 798 Covered T4,T8,T9
TransmitHold->AcquireStart 962 Covered T22,T23
TransmitHold->Idle 960 Covered T22,T23
TransmitHold->TransmitAck 775 Covered T4,T8,T9
TransmitHold->TransmitSetup 779 Covered T4,T8,T9
TransmitPulse->AcquireStart 962 Covered T4,T16,T17
TransmitPulse->Idle 960 Covered T4,T16,T17
TransmitPulse->TransmitHold 766 Covered T4,T8,T9
TransmitSetup->AcquireStart 962 Covered T22,T23
TransmitSetup->Idle 960 Covered T22,T23
TransmitSetup->TransmitPulse 761 Covered T4,T8,T9
TransmitWait->AcquireStart 962 Covered T22,T23
TransmitWait->Idle 960 Covered T22,T23
TransmitWait->StretchTx 754 Covered T4,T8,T21
TransmitWait->TransmitSetup 756 Covered T4,T8,T9
WaitForStop->AcquireStart 962 Covered T4,T8,T9
WaitForStop->Idle 960 Covered T4,T8,T9



Branch Coverage for Module : i2c_target_fsm
Line No.TotalCoveredPercent
Branches 162 124 76.54
IF 124 6 4 66.67
IF 137 2 2 100.00
IF 147 3 3 100.00
IF 158 3 3 100.00
IF 175 2 2 100.00
IF 184 2 2 100.00
IF 193 2 2 100.00
IF 209 5 5 100.00
IF 232 5 5 100.00
IF 243 4 4 100.00
IF 295 3 3 100.00
CASE 341 44 32 72.73
IF 598 4 3 75.00
CASE 645 69 47 68.12
IF 951 4 3 75.00
IF 975 2 2 100.00
IF 984 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 124 if (load_tcount) -2-: 125 case (tcount_sel) -3-: 131 if (target_enable_i)

Branches:
-1--2--3-StatusTests
1 tSetupData - Covered T4,T8,T21
1 tHoldData - Covered T4,T8,T9
1 tNoDelay - Not Covered
1 default - Not Covered
0 - 1 Covered T4,T8,T9
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 137 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 147 if ((!rst_ni)) -2-: 149 if (actively_stretching)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T8,T21
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 158 if ((!rst_ni)) -2-: 160 if ((auto_ack_load_i && ack_ctrl_stretching))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T8,T11,T12
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 175 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 184 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 193 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 209 if ((!rst_ni)) -2-: 211 if (start_detect_i) -3-: 213 if ((scl_i_q && (!scl_i))) -4-: 216 if ((input_byte_clr || bit_ack))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 1 Covered T2,T3,T4
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 232 if ((!rst_ni)) -2-: 234 if (input_byte_clr) -3-: 236 if (((!scl_i_q) && scl_i)) -4-: 237 if ((!bit_ack))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T4,T8,T9
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T2,T3,T4
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 243 if ((!rst_ni)) -2-: 245 if (((!scl_i_q) && scl_i)) -3-: 246 if (bit_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T2,T3,T4
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 295 if ((!rst_ni)) -2-: 297 if ((bit_ack && address_match))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T8,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 341 case (state_q) -2-: 369 if (bit_ack) -3-: 370 if (address_match) -4-: 380 if (scl_i) -5-: 402 if ((tcount_q == 16'b1)) -6-: 403 if (nack_transaction_q) -7-: 407 if ((!stretch_addr)) -8-: 412 if (restart_det_q) -9-: 448 if ((!scl_i)) -10-: 466 if (scl_i) -11-: 487 if ((tcount_q == 16'b1)) -12-: 500 if (nack_timeout) -13-: 523 if (nack_timeout) -14-: 530 if ((!stretch_addr)) -15-: 532 if (restart_det_q) -16-: 545 if (nack_timeout) -17-: 566 if ((nack_timeout || (sw_nack_i && (!can_auto_ack))))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTests
Idle - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireStart - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrRead 1 1 - - - - - - - - - - - - - - Covered T4,T8,T9
AddrRead 1 0 - - - - - - - - - - - - - - Covered T30,T31,T32
AddrRead 0 - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckWait - - 1 - - - - - - - - - - - - - Not Covered
AddrAckWait - - 0 - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckSetup - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckPulse - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckHold - - - 1 1 - - - - - - - - - - - Not Covered
AddrAckHold - - - 1 0 1 - - - - - - - - - - Covered T4,T8,T9
AddrAckHold - - - 1 0 0 - - - - - - - - - - Covered T18,T19,T20
AddrAckHold - - - 1 - - 1 - - - - - - - - - Covered T4,T8,T9
AddrAckHold - - - 1 - - 0 - - - - - - - - - Covered T4,T8,T9
AddrAckHold - - - 0 - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitSetup - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitPulse - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitHold - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitAck - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitAckPulse - - - - - - - 1 - - - - - - - - Covered T4,T8,T9
TransmitAckPulse - - - - - - - 0 - - - - - - - - Covered T4,T8,T9
WaitForStop - - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireByte - - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckWait - - - - - - - - 1 - - - - - - - Not Covered
AcquireAckWait - - - - - - - - 0 - - - - - - - Covered T4,T8,T9
AcquireAckSetup - - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckPulse - - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckHold - - - - - - - - - 1 - - - - - - Covered T4,T8,T9
AcquireAckHold - - - - - - - - - 0 - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - 1 - - - - - Not Covered
StretchAddrAck - - - - - - - - - - 0 - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - 1 - - - - Not Covered
StretchAddr - - - - - - - - - - - 0 1 1 - - Covered T18,T19,T20
StretchAddr - - - - - - - - - - - 0 1 0 - - Covered T19,T33,T34
StretchAddr - - - - - - - - - - - 0 0 - - - Covered T18,T19,T20
StretchTx - - - - - - - - - - - - - - 1 - Not Covered
StretchTx - - - - - - - - - - - - - - 0 - Covered T4,T8,T21
StretchTxSetup - - - - - - - - - - - - - - - - Covered T4,T8,T21
StretchAcqFull - - - - - - - - - - - - - - - 1 Not Covered
StretchAcqFull - - - - - - - - - - - - - - - 0 Covered T8,T11,T12
StretchAcqSetup - - - - - - - - - - - - - - - - Covered T8,T11,T12
default - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 598 if ((target_enable_i && stop_detect_i)) -2-: 605 if (nack_transaction_q) -3-: 610 if ((target_enable_i && start_detect_i))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 - Covered T4,T8,T9
0 - 1 Covered T4,T8,T9
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 645 case (state_q) -2-: 657 if ((!scl_i)) -3-: 666 if (bit_ack) -4-: 667 if (address_match) -5-: 680 if (scl_i) -6-: 683 if ((tcount_q == 16'b1)) -7-: 684 if ((!nack_addr_after_timeout_i)) -8-: 688 if (nack_transaction_q) -9-: 696 if (stretch_addr) -10-: 710 if (scl_i) -11-: 714 if ((!scl_i)) -12-: 722 if ((tcount_q == 16'b1)) -13-: 728 if (nack_transaction_q) -14-: 735 if (stretch_addr) -15-: 742 if (rw_bit_q) -16-: 753 if (stretch_tx) -17-: 761 if (scl_i) -18-: 765 if ((!scl_i)) -19-: 773 if ((tcount_q == 16'b1)) -20-: 774 if (bit_ack) -21-: 785 if (scl_i) -22-: 792 if ((!scl_i)) -23-: 794 if (host_ack) -24-: 810 if (bit_ack) -25-: 818 if (scl_i) -26-: 821 if ((tcount_q == 16'b1)) -27-: 822 if (nack_transaction_q) -28-: 824 if (stretch_rx) -29-: 836 if (scl_i) -30-: 840 if ((!scl_i)) -31-: 848 if ((tcount_q == 16'b1)) -32-: 857 if (nack_timeout) -33-: 859 if ((!stretch_addr)) -34-: 868 if ((tcount_q == 16'b1)) -35-: 877 if (nack_timeout) -36-: 879 if ((!stretch_addr)) -37-: 885 (rw_bit_q) ? -38-: 892 if (nack_timeout) -39-: 894 if ((!stretch_tx)) -40-: 911 if ((tcount_q == 16'b1)) -41-: 923 if ((nack_timeout || (sw_nack_i && (!can_auto_ack)))) -42-: 925 if ((~stretch_rx)) -43-: 934 if ((tcount_q == 16'b1))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40--41--42--43-StatusTests
Idle - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireStart 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireStart 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrRead - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrRead - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T30,T31,T32
AddrRead - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckWait - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckWait - - - 0 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckSetup - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckSetup - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckPulse - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckPulse - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckHold - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - - - - - - - - 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T18,T19,T20
AddrAckHold - - - - - - - - - - 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckHold - - - - - - - - - - 1 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AddrAckHold - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T21
TransmitWait - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitSetup - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitSetup - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitPulse - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitPulse - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitHold - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitHold - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitHold - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitAck - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitAck - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
WaitForStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireByte - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireByte - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 1 - - - - - - - - - - - - - - - Covered T8,T11,T12
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 0 - - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - - - - - - - - Not Covered
AcquireAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckPulse - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckPulse - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckHold - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - Covered T4,T8,T9
AcquireAckHold - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 - - - - - - Covered T18,T19,T20
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - Covered T18,T19,T20
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - Not Covered
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - Covered T4,T8,T21
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - Covered T4,T8,T21
StretchTxSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - Covered T4,T8,T21
StretchTxSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Covered T4,T8,T21
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - Not Covered
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - Covered T8,T11,T12
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - Covered T8,T11,T12
StretchAcqSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T8,T11,T12
StretchAcqSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T8,T11,T12
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 951 if (((!target_idle) && (!target_enable_i))) -2-: 961 if ((target_enable_i && start_detect_i)) -3-: 963 if (stop_detect_i)

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T4,T8,T9
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 975 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 984 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : i2c_target_fsm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AcqDepthRdCheck_A 410395107 3420261 0 0
AcqFifoDeepEnough_A 410395107 410222411 0 0
SclOutputGlitch_A 410395107 57135 0 0


AcqDepthRdCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410395107 3420261 0 0
T4 78778 5777 0 0
T5 36886 0 0 0
T6 75474 0 0 0
T7 696815 0 0 0
T8 100747 223 0 0
T9 127089 450 0 0
T10 15172 0 0 0
T11 38221 88 0 0
T16 0 8413 0 0
T21 138471 766 0 0
T35 0 35388 0 0
T36 0 480 0 0
T37 0 423 0 0
T38 0 392 0 0
T39 31805 0 0 0

AcqFifoDeepEnough_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410395107 410222411 0 0
T1 5286 4888 0 0
T2 46660 46594 0 0
T3 11196 10343 0 0
T4 78778 78723 0 0
T5 36886 36829 0 0
T6 75474 75402 0 0
T7 696815 696760 0 0
T8 100747 100668 0 0
T9 127089 127015 0 0
T10 15172 15090 0 0

SclOutputGlitch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 410395107 57135 0 0
T4 78778 23 0 0
T5 36886 0 0 0
T6 75474 0 0 0
T7 696815 0 0 0
T8 100747 93 0 0
T9 127089 0 0 0
T10 15172 0 0 0
T11 38221 20 0 0
T12 0 62 0 0
T16 0 48 0 0
T21 138471 45 0 0
T35 0 104 0 0
T36 0 289 0 0
T37 0 345 0 0
T38 0 94 0 0
T39 31805 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%