Unified Coverage Report :: Module :: i2c_controller_fsm

Module : i2c_controller_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.94	94.79	86.67		90.91	92.35	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_i2c_controller_fsm	92.94	94.79	86.67		90.91	92.35	100.00

---

Module Instance : tb.dut.i2c_core.u_i2c_controller_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.94	94.79	86.67		90.91	92.35	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.94	94.79	86.67		90.91	92.35	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.03	97.30	71.15			91.67	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_controller_fsm

	Line No.	Total	Covered	Percent
TOTAL		403	382	94.79
ALWAYS	118	15	15	100.00
ALWAYS	143	3	3	100.00
ALWAYS	156	5	5	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	183	6	6	100.00
ALWAYS	199	9	8	88.89
CONT_ASSIGN	214	1	1	100.00
ALWAYS	218	7	7	100.00
ALWAYS	231	6	6	100.00
ALWAYS	242	5	5	100.00
ALWAYS	249	7	7	100.00
ALWAYS	262	5	5	100.00
ALWAYS	276	8	8	100.00
ALWAYS	288	8	7	87.50
ALWAYS	300	3	3	100.00
CONT_ASSIGN	342	1	1	100.00
ALWAYS	347	6	6	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	367	1	1	100.00
ALWAYS	372	119	115	96.64
ALWAYS	575	180	165	91.67
ALWAYS	909	3	3	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	917	1	1	100.00
CONT_ASSIGN	920	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
119	1	1
120	1	1
121	1	1
122	1	1
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
133	1	1
138	1	1
			MISSING_ELSE
143	1	1
144	1	1
146	1	1
156	1	1
157	1	1
158	1	1
160	1	1
162	1	1
179	1	1
183	1	1
184	1	1
186	1	1
187	1	1
188	1	1
189	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
204	1	1
205	1	1
206	0	1
			MISSING_ELSE
209	1	1
210	1	1
214	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
225	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
242	2	2
243	2	2
244	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
256	1	1
262	1	1
263	1	1
264	1	1
266	1	1
267	1	1
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
			MISSING_ELSE
288	1	1
289	1	1
290	1	1
291	0	1
292	1	1
293	1	1
294	1	1
295	1	1
			MISSING_ELSE
300	1	1
301	1	1
303	1	1
342	1	1
347	1	1
348	1	1
349	1	1
353	1	1
354	1	1
355	1	1
			MISSING_ELSE
363	1	1
367	1	1
372	1	1
373	1	1
374	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
388	1	1
389	1	1
390	1	1
391	1	1
393	1	1
394	1	1
404	1	1
405	1	1
406	1	1
407	2	2
			MISSING_ELSE
411	1	1
412	1	1
413	1	1
417	1	1
418	1	1
419	1	1
422	1	1
423	1	1
424	1	1
426	1	1
428	1	1
432	1	1
433	1	1
434	1	1
435	1	1
436	1	2
			MISSING_ELSE
437	2	2
			MISSING_ELSE
441	1	1
442	1	1
443	1	1
447	1	1
448	1	1
449	1	1
453	1	1
454	1	1
455	1	1
456	2	2
			MISSING_ELSE
457	1	1
458	1	2
			MISSING_ELSE
459	2	2
			MISSING_ELSE
463	1	1
464	1	1
465	1	1
469	1	1
470	1	1
471	1	1
475	1	1
476	1	1
477	1	1
478	1	2
			MISSING_ELSE
479	2	2
			MISSING_ELSE
483	1	1
484	1	1
485	1	1
486	1	1
487	1	1
			MISSING_ELSE
492	1	1
493	1	1
497	2	2
498	2	2
499	1	1
503	1	1
504	2	2
505	2	2
506	1	1
507	1	1
508	1	1
509	1	2
			MISSING_ELSE
510	2	2
			MISSING_ELSE
514	1	1
515	2	2
516	2	2
517	1	1
518	1	1
522	1	1
523	1	1
524	1	1
528	1	1
529	1	1
530	1	1
534	1	1
535	1	1
536	1	1
537	1	1
541	1	1
547	1	1
551	1	1
552	2	2
553	1	1
554	1	1
575	1	1
576	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
583	1	1
584	1	1
585	1	1
586	1	1
587	1	1
588	1	1
590	1	1
594	1	1
595	1	1
608	1	1
610	0	1
611	0	1
612	0	1
613	0	1
			MISSING_ELSE
615	1	1
616	1	1
617	1	1
			MISSING_ELSE
			MISSING_ELSE
620	1	1
621	0	1
622	0	1
623	0	1
624	0	1
			MISSING_ELSE
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
			MISSING_ELSE
643	1	1
644	1	1
645	1	1
646	1	1
			MISSING_ELSE
651	1	1
652	1	1
653	1	1
654	1	1
			MISSING_ELSE
659	1	1
660	1	1
661	1	1
662	1	1
663	1	1
664	1	1
666	1	1
667	1	1
			MISSING_ELSE
673	1	1
674	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
681	1	1
			MISSING_ELSE
686	1	1
687	1	1
688	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
695	1	1
696	1	1
			MISSING_ELSE
703	1	1
704	1	1
705	1	1
706	1	1
			MISSING_ELSE
711	1	1
713	1	1
714	1	1
716	1	1
717	1	1
718	1	1
719	1	1
			MISSING_ELSE
725	1	1
726	1	1
727	1	1
728	1	1
729	1	1
731	1	1
732	1	1
733	1	1
			MISSING_ELSE
739	1	1
740	1	1
741	1	1
742	1	1
			MISSING_ELSE
747	1	1
749	1	1
750	1	1
751	1	1
752	1	1
753	1	1
754	1	1
755	1	1
			MISSING_ELSE
760	1	1
761	1	1
762	1	1
763	1	1
764	1	1
765	1	1
766	1	1
768	1	1
769	1	1
			MISSING_ELSE
776	1	1
777	1	1
778	1	1
779	1	1
780	1	1
			MISSING_ELSE
785	1	1
786	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
807	1	1
808	1	1
809	1	1
812	1	1
813	1	1
814	1	1
815	1	1
			MISSING_ELSE
821	1	1
822	1	1
823	1	1
824	1	1
			MISSING_ELSE
829	1	1
830	1	1
831	1	1
			MISSING_ELSE
836	1	1
837	1	1
838	1	1
839	1	1
840	1	1
842	0	1
843	0	1
844	0	1
846	1	1
847	1	1
848	1	1
			MISSING_ELSE
854	1	1
855	1	1
856	1	1
857	1	1
858	1	1
859	1	1
860	1	1
861	1	1
862	1	1
864	1	1
865	1	1
866	1	1
867	1	1
872	1	1
873	0	1
874	0	1
875	0	1
876	0	1
877	1	1
879	1	1
880	1	1
881	1	1
883	1	1
884	1	1
885	1	1
909	1	1
910	1	1
912	1	1
916	1	1
917	1	1
920	1	1

---

Cond Coverage for Module : i2c_controller_fsm

	Total	Covered	Percent
Conditions	165	143	86.67
Logical	165	143	86.67
Non-Logical	0	0
Event	0	0

 LINE       133
 EXPRESSION (host_enable_i || (((!host_idle_o)) && ((!host_enable_i))))
             ------1------    --------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T47,T48,T49
1	0	Covered	T1,T2,T3

 LINE       133
 SUB-EXPRESSION (((!host_idle_o)) && ((!host_enable_i)))
                 --------1-------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T48,T49

 LINE       158
 EXPRESSION (stretch_en && ((!scl_i)))
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       186
 EXPRESSION (stretch_idle_cnt == stretch_cnt_threshold)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (fmt_byte_i == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T7,T43,T71

 LINE       278
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T48,T82,T83

 LINE       290
 EXPRESSION (pend_restart && ((!host_enable_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T7
1	1	Not Covered

 LINE       349
 EXPRESSION (((!en_sda_interf_det)) && ((|sda_rise_cnt)))
             -----------1----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       354
 EXPRESSION (en_sda_interf_det && (sda_rise_cnt < sda_rise_latency))
             --------1--------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       363
 EXPRESSION ((sda_rise_cnt == sda_rise_latency) & sda_o & ((!sda_i)))
             -----------------1----------------   --2--   -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       363
 SUB-EXPRESSION (sda_rise_cnt == sda_rise_latency)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       367
 EXPRESSION (unhandled_unexp_nak_i && host_enable_i && (state_q == Idle) && host_nack_handler_timeout_en_i && ((!unhandled_nak_timeout_i)))
             ----------1----------    ------2------    --------3--------    ---------------4--------------    --------------5-------------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T2,T5,T39
1	0	1	1	1	Not Covered
1	1	0	1	1	Covered	T2,T5,T39
1	1	1	0	1	Not Covered
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T2,T5,T39

 LINE       367
 SUB-EXPRESSION (state_q == Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       437
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       456
 EXPRESSION (((!scl_i_q)) && scl_i && sda_i && ((!fmt_flag_nak_ok_i)))
             ------1-----    --2--    --3--    -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T5,T39
1	0	1	1	Covered	T2,T3,T5
1	1	0	1	Covered	T2,T5,T6
1	1	1	0	Covered	T2,T5,T39
1	1	1	1	Covered	T2,T5,T39

 LINE       458
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T5,T6
1	1	Not Covered

 LINE       459
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       478
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Not Covered

 LINE       479
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       485
 EXPRESSION ((bit_index == '0) && (tcount_q == 16'b1))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       485
 SUB-EXPRESSION (bit_index == '0)
                --------1--------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       485
 SUB-EXPRESSION (tcount_q == 16'b1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       498
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       505
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       509
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Not Covered

 LINE       510
 EXPRESSION (sda_i_q != sda_i)
            ---------1--------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T5,T47,T43

 LINE       516
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       547
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T50,T84,T85
1	0	Covered	T2,T5,T7
1	1	Covered	T1,T2,T3

 LINE       595
 EXPRESSION (unhandled_unexp_nak_i || unhandled_nak_timeout_i || halt_controller_i)
             ----------1----------    -----------2-----------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       608
 EXPRESSION (trans_started && unhandled_nak_cnt_expired)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T39
1	1	Not Covered

 LINE       616
 EXPRESSION (trans_started || bus_free_i)
             ------1------    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T86,T87,T88
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       620
 EXPRESSION (trans_started && ((!host_enable_i)))
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       634
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       643
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       651
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T43,T44,T45
1	Covered	T1,T2,T3

 LINE       660
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       674
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T89,T90

 LINE       678
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       687
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       691
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       703
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       711
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       716
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T5,T6

 LINE       725
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       739
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       747
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T45,T89,T90

 LINE       751
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       760
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       763
 EXPRESSION (bit_index == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       777
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       786
 EXPRESSION (((!scl_i)) && stretch_predict_cnt_expired)
             -----1----    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T48,T45,T89

 LINE       790
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       799
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       801
 EXPRESSION (byte_index == 9'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       821
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       829
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       837
 EXPRESSION (scl_i && sda_i)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       859
 EXPRESSION (fmt_flag_start_before_i && ((!trans_started)))
             -----------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T50,T84,T85
1	0	Covered	T2,T5,T7
1	1	Covered	T1,T2,T3

 LINE       872
 EXPRESSION (((!host_enable_i)) && trans_started)
             ---------1--------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T47,T48,T49
1	1	Not Covered

 LINE       877
 EXPRESSION (((!host_enable_i)) || (fmt_fifo_depth_i == 7'b1) || unhandled_unexp_nak_i || ((!trans_started)))
             ---------1--------    -------------2------------    ----------3----------    ---------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T2,T5,T6
0	0	0	1	Not Covered
0	0	1	0	Covered	T2,T5,T39
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       877
 SUB-EXPRESSION (fmt_fifo_depth_i == 7'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       920
 EXPRESSION (stretch_en && timeout_enable_i && (stretch_idle_cnt > 31'(stretch_timeout_i)))
             -----1----    --------2-------    ---------------------3---------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : i2c_controller_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	33	30	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Active	617	Covered	T1,T2,T3
ClockLow	652	Covered	T1,T2,T3
ClockLowAck	692	Covered	T2,T3,T5
ClockPulse	666	Covered	T1,T2,T3
ClockPulseAck	704	Covered	T2,T3,T5
ClockStart	644	Covered	T1,T2,T3
ClockStop	611	Covered	T2,T5,T6
HoldBit	679	Covered	T1,T2,T3
HoldDevAck	717	Covered	T2,T5,T6
HoldStart	635	Covered	T1,T2,T3
HoldStop	830	Covered	T2,T5,T6
HostClockLowAck	764	Covered	T2,T5,T6
HostClockPulseAck	778	Covered	T2,T5,T6
HostHoldBitAck	791	Covered	T2,T5,T6
Idle	842	Covered	T1,T2,T3
PopFmtFifo	731	Covered	T2,T5,T6
ReadClockLow	768	Covered	T2,T5,T6
ReadClockPulse	740	Covered	T2,T5,T6
ReadHoldBit	752	Covered	T2,T5,T6
SetupStart	663	Covered	T1,T2,T3
SetupStop	822	Covered	T2,T5,T6

transitions	Line No.	Covered	Tests
Active->ClockLow	864	Covered	T2,T5,T6
Active->ReadClockLow	856	Covered	T2,T5,T6
Active->SetupStart	860	Covered	T1,T2,T3
ClockLow->ClockPulse	666	Covered	T1,T2,T3
ClockLow->SetupStart	663	Covered	T2,T5,T7
ClockLowAck->ClockPulseAck	704	Covered	T2,T3,T5
ClockPulse->HoldBit	679	Covered	T1,T2,T3
ClockPulseAck->HoldDevAck	717	Covered	T2,T5,T6
ClockStart->ClockLow	652	Covered	T1,T2,T3
ClockStop->SetupStop	822	Covered	T2,T5,T6
HoldBit->ClockLow	695	Covered	T1,T2,T3
HoldBit->ClockLowAck	692	Covered	T2,T3,T5
HoldDevAck->ClockStop	727	Covered	T5,T6,T39
HoldDevAck->PopFmtFifo	731	Covered	T2,T5,T6
HoldStart->ClockStart	644	Covered	T1,T2,T3
HoldStop->Idle	842	Not Covered
HoldStop->PopFmtFifo	846	Covered	T2,T5,T6
HostClockLowAck->HostClockPulseAck	778	Covered	T2,T5,T6
HostClockPulseAck->HostHoldBitAck	791	Covered	T2,T5,T6
HostHoldBitAck->ClockStop	803	Covered	T2,T5,T6
HostHoldBitAck->PopFmtFifo	807	Covered	T2,T5,T7
HostHoldBitAck->ReadClockLow	812	Covered	T2,T5,T6
Idle->Active	617	Covered	T1,T2,T3
Idle->ClockStop	611	Not Covered
PopFmtFifo->Active	883	Covered	T2,T5,T6
PopFmtFifo->ClockStop	874	Not Covered
PopFmtFifo->Idle	879	Covered	T2,T5,T6
ReadClockLow->ReadClockPulse	740	Covered	T2,T5,T6
ReadClockPulse->ReadHoldBit	752	Covered	T2,T5,T6
ReadHoldBit->HostClockLowAck	764	Covered	T2,T5,T6
ReadHoldBit->ReadClockLow	768	Covered	T2,T5,T6
SetupStart->HoldStart	635	Covered	T1,T2,T3
SetupStop->HoldStop	830	Covered	T2,T5,T6

---

Branch Coverage for Module : i2c_controller_fsm

	Line No.	Total	Covered	Percent
Branches		170	157	92.35
IF	119	13	12	92.31
IF	143	2	2	100.00
IF	156	3	3	100.00
IF	183	4	4	100.00
IF	199	4	3	75.00
IF	218	4	4	100.00
IF	231	4	4	100.00
IF	242	3	3	100.00
IF	249	4	4	100.00
IF	262	2	2	100.00
IF	276	5	5	100.00
IF	288	5	4	80.00
IF	300	2	2	100.00
IF	347	4	4	100.00
CASE	383	48	43	89.58
CASE	590	61	56	91.80
IF	909	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_controller_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	119	if (load_tcount)
-2-:	120	case (tcount_sel)
-3-:	133	if ((host_enable_i || ((!host_idle_o) && (!host_enable_i))))

Branches:

-1-	-2-	-3-	Status	Tests
1	tSetupStart	-	Covered	T1,T2,T3
1	tHoldStart	-	Covered	T1,T2,T3
1	tClockStart	-	Covered	T1,T2,T3
1	tClockLow	-	Covered	T1,T2,T3
1	tClockPulse	-	Covered	T1,T2,T3
1	tClockHigh	-	Covered	T2,T3,T5
1	tHoldBit	-	Covered	T1,T2,T3
1	tClockStop	-	Covered	T2,T5,T6
1	tSetupStop	-	Covered	T2,T5,T6
1	tNoDelay	-	Covered	T2,T5,T6
1	default	-	Not Covered
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	if ((!rst_ni))
-2-:	158	if ((stretch_en && (!scl_i)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if ((stretch_idle_cnt == stretch_cnt_threshold))
-3-:	188	if ((!stretch_en))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	199	if ((!rst_ni))
-2-:	202	if (incr_nak_cnt)
-3-:	205	if ((unhandled_nak_cnt > host_nack_handler_timeout_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Not Covered
0	1	0	Covered	T2,T5,T39
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if (bit_clr)
-3-:	222	if (bit_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if ((!rst_ni))
-2-:	233	if (read_byte_clr)
-3-:	235	if (shift_data_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	if ((!fmt_flag_read_bytes_i))
-2-:	243	if ((fmt_byte_i == '0))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T43,T71
0	0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	249	if ((!rst_ni))
-2-:	251	if (byte_clr)
-3-:	253	if (byte_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	262	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	276	if ((!rst_ni))
-2-:	278	if ((trans_started && (!host_enable_i)))
-3-:	280	if (log_start)
-4-:	282	if (log_stop)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T48,T82,T83
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T5,T6
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))
-2-:	290	if ((pend_restart && (!host_enable_i)))
-3-:	292	if (req_restart)
-4-:	294	if (log_start)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Covered	T2,T5,T7
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	if ((!rst_ni))
-2-:	349	if (((!en_sda_interf_det) && (|sda_rise_cnt)))
-3-:	354	if ((en_sda_interf_det && (sda_rise_cnt < sda_rise_latency)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	383	case (state_q)
-2-:	389	if (trans_started)
-3-:	407	if (log_start)
-4-:	423	if (pend_restart)
-5-:	436	if ((scl_i_q && (!scl_i)))
-6-:	437	if ((sda_i_q != sda_i))
-7-:	456	if (((((!scl_i_q) && scl_i) && sda_i) && (!fmt_flag_nak_ok_i)))
-8-:	458	if ((scl_i_q && (!scl_i)))
-9-:	459	if ((sda_i_q != sda_i))
-10-:	478	if ((scl_i_q && (!scl_i)))
-11-:	479	if ((sda_i_q != sda_i))
-12-:	485	if (((bit_index == '0) && (tcount_q == 16'b1)))
-13-:	497	if (fmt_flag_read_continue_i)
-14-:	498	if ((byte_index == 9'b1))
-15-:	504	if (fmt_flag_read_continue_i)
-16-:	505	if ((byte_index == 9'b1))
-17-:	509	if ((scl_i_q && (!scl_i)))
-18-:	510	if ((sda_i_q != sda_i))
-19-:	515	if (fmt_flag_read_continue_i)
-20-:	516	if ((byte_index == 9'b1))
-21-:	552	if (fmt_flag_stop_after_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T39
Idle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockStart	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockLow	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T7
ClockLow	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulse	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulse	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulse	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
ClockPulse	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
ClockPulseAck	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T39
ClockPulseAck	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
ClockPulseAck	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClockPulseAck	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
ClockPulseAck	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
ClockPulseAck	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ReadClockPulse	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T7
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T5,T7
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T5,T47,T43
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T2,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T5,T7
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T5,T6
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T6
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	590	case (state_q)
-2-:	594	if (host_enable_i)
-3-:	595	if (((unhandled_unexp_nak_i || unhandled_nak_timeout_i) || halt_controller_i))
-4-:	608	if ((trans_started && unhandled_nak_cnt_expired))
-5-:	615	if (fmt_fifo_rvalid_i)
-6-:	616	if ((trans_started || bus_free_i))
-7-:	620	if ((trans_started && (!host_enable_i)))
-8-:	634	if ((tcount_q == 16'b1))
-9-:	643	if ((tcount_q == 16'b1))
-10-:	651	if ((tcount_q == 16'b1))
-11-:	660	if ((tcount_q == 16'b1))
-12-:	662	if (pend_restart)
-13-:	674	if (((!scl_i) && stretch_predict_cnt_expired))
-14-:	678	if ((tcount_q == 16'b1))
-15-:	687	if ((tcount_q == 16'b1))
-16-:	691	if ((bit_index == '0))
-17-:	703	if ((tcount_q == 16'b1))
-18-:	711	if (((!scl_i) && stretch_predict_cnt_expired))
-19-:	716	if ((tcount_q == 16'b1))
-20-:	725	if ((tcount_q == 16'b1))
-21-:	726	if (fmt_flag_stop_after_i)
-22-:	739	if ((tcount_q == 16'b1))
-23-:	747	if (((!scl_i) && stretch_predict_cnt_expired))
-24-:	751	if ((tcount_q == 16'b1))
-25-:	760	if ((tcount_q == 16'b1))
-26-:	763	if ((bit_index == '0))
-27-:	777	if ((tcount_q == 16'b1))
-28-:	786	if (((!scl_i) && stretch_predict_cnt_expired))
-29-:	790	if ((tcount_q == 16'b1))
-30-:	799	if ((tcount_q == 16'b1))
-31-:	801	if ((byte_index == 9'b1))
-32-:	802	if (fmt_flag_stop_after_i)
-33-:	821	if ((tcount_q == 16'b1))
-34-:	829	if ((tcount_q == 16'b1))
-35-:	837	if ((scl_i && sda_i))
-36-:	840	if (auto_stop_q)
-37-:	854	if (fmt_flag_read_bytes_i)
-38-:	859	if ((fmt_flag_start_before_i && (!trans_started)))
-39-:	872	if (((!host_enable_i) && trans_started))
-40-:	877	if (((((!host_enable_i) || (fmt_fifo_depth_i == 7'b1)) || unhandled_unexp_nak_i) || (!trans_started)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
Idle	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T39
Idle	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T86,T87,T88
Idle	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SetupStart	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldStart	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldStart	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockStart	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockStart	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T43,T44,T45
ClockLow	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T7
ClockLow	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockLow	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulse	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T89,T90
ClockPulse	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockPulse	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
HoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
ClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T39
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HoldDevAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadClockLow	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T89,T90
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadClockPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ReadHoldBit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostClockLowAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T48,T45,T89
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostClockPulseAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Covered	T2,T5,T7
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
HostHoldBitAck	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T5,T6
ClockStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T5,T6
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T5,T6
SetupStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T5,T6
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	Not Covered
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T2,T5,T6
HoldStop	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T5,T6
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T5,T6
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T3
Active	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T5,T6
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T5,T6
PopFmtFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	909	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_controller_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SclOutputGlitch_A	410395107	5346719	0	0

SclOutputGlitch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410395107	5346719	0	0
T1	5286	9	0	0
T2	46660	1791	0	0
T3	11196	61	0	0
T4	78778	0	0	0
T5	36886	1415	0	0
T6	75474	3784	0	0
T7	696815	5071	0	0
T8	100747	0	0	0
T9	127089	0	0	0
T10	15172	586	0	0
T39	0	1103	0	0
T47	0	10325	0	0
T60	0	7081	0	0