Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	405049710	0	0	0
ctrl_rd_A	405049710	2374	0	0
host_fifo_config_rd_A	405049710	6176	0	0
host_nack_handler_timeout_rd_A	405049710	1524	0	0
host_timeout_ctrl_rd_A	405049710	1563	0	0
intr_enable_rd_A	405049710	3748	0	0
ovrd_rd_A	405049710	2634	0	0
target_fifo_config_rd_A	405049710	1535	0	0
target_id_rd_A	405049710	1939	0	0
target_timeout_ctrl_rd_A	405049710	1711	0	0
timeout_ctrl_rd_A	405049710	1961	0	0
timing0_rd_A	405049710	1739	0	0
timing1_rd_A	405049710	1728	0	0
timing2_rd_A	405049710	1705	0	0
timing3_rd_A	405049710	1773	0	0
timing4_rd_A	405049710	1632	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	2374	0	0
T88	2123	5	0	0
T89	2605	30	0	0
T90	3221	7	0	0
T91	2666	12	0	0
T92	3479	11	0	0
T93	14526	133	0	0
T94	2419	24	0	0
T95	6421	56	0	0
T96	2576	39	0	0
T97	3544	12	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	6176	0	0
T98	291824	111	0	0
T99	0	200	0	0
T100	0	186	0	0
T101	0	142	0	0
T102	0	226	0	0
T103	0	165	0	0
T104	0	116	0	0
T105	0	229	0	0
T106	0	98	0	0
T107	0	222	0	0
T108	9896	0	0	0
T109	265590	0	0	0
T110	905695	0	0	0
T111	149276	0	0	0
T112	71404	0	0	0
T113	9026	0	0	0
T114	69059	0	0	0
T115	138760	0	0	0
T116	5539	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1524	0	0
T88	2123	7	0	0
T90	3221	5	0	0
T91	2666	3	0	0
T92	3479	2	0	0
T93	14526	73	0	0
T94	2419	4	0	0
T95	6421	40	0	0
T96	2576	19	0	0
T97	3544	24	0	0
T117	2297	19	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1563	0	0
T88	2123	7	0	0
T89	2605	11	0	0
T90	3221	13	0	0
T91	2666	3	0	0
T92	3479	13	0	0
T93	14526	21	0	0
T94	2419	6	0	0
T95	6421	36	0	0
T96	2576	6	0	0
T97	3544	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	3748	0	0
T88	0	3	0	0
T89	0	56	0	0
T106	0	34	0	0
T118	203177	14	0	0
T119	0	9	0	0
T120	0	40	0	0
T121	0	23	0	0
T122	0	7	0	0
T123	0	5	0	0
T124	0	12	0	0
T125	1962	0	0	0
T126	11740	0	0	0
T127	3531	0	0	0
T128	231542	0	0	0
T129	616623	0	0	0
T130	15151	0	0	0
T131	17049	0	0	0
T132	208326	0	0	0
T133	1273	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	2634	0	0
T29	54613	0	0	0
T34	256033	0	0	0
T41	123577	0	0	0
T44	3064	43	0	0
T45	15918	0	0	0
T51	0	69	0	0
T52	4330	0	0	0
T55	215366	0	0	0
T134	0	70	0	0
T135	0	25	0	0
T136	0	17	0	0
T137	0	63	0	0
T138	0	41	0	0
T139	0	48	0	0
T140	0	45	0	0
T141	0	52	0	0
T142	301407	0	0	0
T143	916	0	0	0
T144	12668	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1535	0	0
T88	2123	4	0	0
T90	3221	7	0	0
T91	2666	15	0	0
T92	3479	37	0	0
T93	14526	50	0	0
T94	2419	2	0	0
T95	6421	4	0	0
T96	2576	12	0	0
T97	3544	4	0	0
T117	2297	10	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1939	0	0
T88	2123	9	0	0
T89	2605	16	0	0
T90	3221	7	0	0
T91	2666	17	0	0
T92	3479	76	0	0
T93	14526	93	0	0
T94	2419	13	0	0
T95	6421	67	0	0
T96	2576	3	0	0
T97	3544	32	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1711	0	0
T88	2123	4	0	0
T89	2605	16	0	0
T90	3221	26	0	0
T91	2666	13	0	0
T92	3479	26	0	0
T93	14526	44	0	0
T94	2419	6	0	0
T95	6421	64	0	0
T96	2576	5	0	0
T97	3544	19	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1961	0	0
T88	2123	4	0	0
T89	2605	9	0	0
T90	3221	21	0	0
T91	2666	1	0	0
T92	3479	32	0	0
T93	14526	76	0	0
T94	2419	5	0	0
T95	6421	55	0	0
T96	2576	3	0	0
T97	3544	32	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1739	0	0
T88	2123	1	0	0
T89	2605	11	0	0
T90	3221	14	0	0
T91	2666	15	0	0
T92	3479	39	0	0
T93	14526	77	0	0
T94	2419	4	0	0
T95	6421	70	0	0
T96	2576	12	0	0
T97	3544	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1728	0	0
T88	2123	9	0	0
T89	2605	2	0	0
T90	3221	17	0	0
T91	2666	1	0	0
T92	3479	31	0	0
T93	14526	97	0	0
T94	2419	17	0	0
T95	6421	42	0	0
T96	2576	20	0	0
T97	3544	61	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1705	0	0
T88	2123	7	0	0
T89	2605	10	0	0
T90	3221	3	0	0
T91	2666	8	0	0
T92	3479	21	0	0
T93	14526	61	0	0
T94	2419	8	0	0
T95	6421	71	0	0
T96	2576	14	0	0
T97	3544	18	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1773	0	0
T88	2123	6	0	0
T89	2605	4	0	0
T90	3221	20	0	0
T91	2666	35	0	0
T92	3479	23	0	0
T93	14526	50	0	0
T94	2419	10	0	0
T95	6421	55	0	0
T96	2576	2	0	0
T97	3544	26	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405049710	1632	0	0
T88	2123	3	0	0
T89	2605	2	0	0
T90	3221	18	0	0
T91	2666	12	0	0
T92	3479	18	0	0
T93	14526	78	0	0
T94	2419	11	0	0
T95	6421	29	0	0
T96	2576	9	0	0
T97	3544	46	0	0