Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.72 100.00 100.00 94.87 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.72 100.00 100.00 94.87 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.72 100.00 100.00 94.87 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.68 97.15 90.83 97.67 83.58 94.42 98.45


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
i2c_core 90.43 96.09 85.91 83.58 91.85 94.74
i2c_csr_assert 93.75 93.75
tlul_assert_device 100.00 100.00 100.00 100.00
u_reg 98.62 98.57 97.01 100.00 97.55 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
129 1 1
130 1 1


Cond Coverage for Module : i2c
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT4,T9,T10
10CoveredT1,T2,T3
11CoveredT4,T10,T170

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 49 45 91.84
Total Bits 390 370 94.87
Total Bits 0->1 195 185 94.87
Total Bits 1->0 195 185 94.87

Ports 49 45 91.84
Port Bits 390 370 94.87
Port Bits 0->1 195 185 94.87
Port Bits 1->0 195 185 94.87

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T52,T41,T35 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T3,T9,T10 Yes T3,T10,T31 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T146,T171,T172 Yes T146,T171,T172 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T10,T170 Yes T4,T10,T170 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T10,T170 Yes T4,T10,T170 OUTPUT
cio_scl_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_sda_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_fmt_threshold_o Yes Yes T2,T3,T58 Yes T1,T2,T3 OUTPUT
intr_rx_threshold_o Yes Yes T2,T3,T58 Yes T2,T3,T58 OUTPUT
intr_acq_threshold_o Yes Yes T7,T12,T19 Yes T7,T12,T19 OUTPUT
intr_rx_overflow_o Yes Yes T54,T55,T56 Yes T54,T55,T56 OUTPUT
intr_controller_halt_o Yes Yes T8,T76,T77 Yes T8,T76,T77 OUTPUT
intr_scl_interference_o Yes Yes T38,T147,T173 Yes T38,T147,T173 OUTPUT
intr_sda_interference_o Yes Yes T2,T3,T57 Yes T2,T3,T57 OUTPUT
intr_stretch_timeout_o Yes Yes T2,T3,T57 Yes T2,T3,T57 OUTPUT
intr_sda_unstable_o Yes Yes T2,T3,T57 Yes T2,T3,T57 OUTPUT
intr_cmd_complete_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_tx_stretch_o Yes Yes T1,T5,T6 Yes T1,T5,T6 OUTPUT
intr_tx_threshold_o Yes Yes T7,T31,T33 Yes T1,T2,T3 OUTPUT
intr_acq_stretch_o Yes Yes T7,T11,T12 Yes T7,T11,T12 OUTPUT
intr_unexp_stop_o Yes Yes T16,T38,T17 Yes T16,T38,T17 OUTPUT
intr_host_timeout_o Yes Yes T46,T38,T47 Yes T46,T38,T47 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : i2c
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 23 23 100.00 23 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 23 23 100.00 23 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 404315798 404137943 0 0
CioSclEnKnownO_A 404315798 404137943 0 0
CioSclKnownO_A 404315798 404137943 0 0
CioSdaEnKnownO_A 404315798 404137943 0 0
CioSdaKnownO_A 404315798 404137943 0 0
FpvSecCmRegWeOnehotCheck_A 404315798 70 0 0
IntrAcqStretchKnownO_A 404315798 404137943 0 0
IntrAcqWtmkKnownO_A 404315798 404137943 0 0
IntrCommandCompleteKnownO_A 404315798 404137943 0 0
IntrControllerHaltKnownO_A 404315798 404137943 0 0
IntrFmtWtmkKnownO_A 404315798 404137943 0 0
IntrHostTimeoutKnownO_A 404315798 404137943 0 0
IntrRxOflwKnownO_A 404315798 404137943 0 0
IntrRxWtmkKnownO_A 404315798 404137943 0 0
IntrSclInterfKnownO_A 404315798 404137943 0 0
IntrSdaInterfKnownO_A 404315798 404137943 0 0
IntrSdaUnstableKnownO_A 404315798 404137943 0 0
IntrStretchTimeoutKnownO_A 404315798 404137943 0 0
IntrTxStretchKnownO_A 404315798 404137943 0 0
IntrTxWtmkKnownO_A 404315798 404137943 0 0
IntrUnexpStopKnownO_A 404315798 404137943 0 0
TlAReadyKnownO_A 404315798 404137943 0 0
TlDValidKnownO_A 404315798 404137943 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

CioSclEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

CioSclKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

CioSdaEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

CioSdaKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 70 0 0
T86 218923 0 0 0
T174 5091 20 0 0
T175 0 20 0 0
T176 0 10 0 0
T177 0 10 0 0
T178 0 10 0 0
T179 54529 0 0 0
T180 229832 0 0 0
T181 101533 0 0 0
T182 80338 0 0 0
T183 27903 0 0 0
T184 3011 0 0 0
T185 14165 0 0 0
T186 67511 0 0 0

IntrAcqStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrAcqWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrCommandCompleteKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrControllerHaltKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrFmtWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrHostTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrRxOflwKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrRxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrSclInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrSdaInterfKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrSdaUnstableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrStretchTimeoutKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrTxStretchKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrTxWtmkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

IntrUnexpStopKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 404315798 404137943 0 0
T1 40896 40833 0 0
T2 212264 212167 0 0
T3 458584 458529 0 0
T4 967 901 0 0
T5 196673 196579 0 0
T6 272230 272162 0 0
T7 82147 82061 0 0
T8 22900 22818 0 0
T9 1343 1267 0 0
T10 1603 1529 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%