Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

173615

1

T7

12

T10

2323

T17

542

ack

14629

1

T7

2

T10

184

T17

11

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	707	1			T10	11		T17	1		T68	5
high	38251	1			T7	4		T10	499		T17	123
med	70524	1			T7	4		T10	936		T17	196
sml	78065	1			T7	6		T10	1053		T17	229
all_zero	697	1			T10	8		T17	4		T68	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93654

1

T7

6

T10

1236

T17

264

auto[1]

94590

1

T7

8

T10

1271

T17

289

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129284

1

T7

11

T10

1698

T17

362

auto[1]

58960

1

T7

3

T10

809

T17

191

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

180471

1

T7

14

T10

2402

T17

543

auto[1]

7773

1

T10

105

T17

10

T54

13

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178048

1

T7

12

T10

2392

T17

544

auto[1]

10196

1

T7

2

T10

115

T17

9

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178953

1

T7

14

T10

2403

T17

548

auto[1]

9291

1

T10

104

T17

5

T54

8

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93654

1

T7

6

T10

1236

T17

264

auto[1]

94590

1

T7

8

T10

1271

T17

289

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129284

1

T7

11

T10

1698

T17

362

auto[1]

58960

1

T7

3

T10

809

T17

191

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

180471

1

T7

14

T10

2402

T17

543

auto[1]

7773

1

T10

105

T17

10

T54

13

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178048

1

T7

12

T10

2392

T17

544

auto[1]

10196

1

T7

2

T10

115

T17

9

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178953

1

T7

14

T10

2403

T17

548

auto[1]

9291

1

T10

104

T17

5

T54

8

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T57

1

T234

1

T235

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T236

1

T237

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T238

1

T239

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

305

1

T10

7

T68

1

T86

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

159

1

T10

2

T54

1

T97

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

152

1

T10

1

T70

1

T86

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

599

1

T10

6

T17

1

T68

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

259

1

T10

2

T68

1

T70

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

285

1

T10

4

T70

1

T97

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

564

1

T10

9

T17

1

T70

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

285

1

T10

2

T17

1

T70

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

286

1

T10

1

T17

1

T70

4

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T104

1

T105

1

T240

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T241

1

T124

1

T242

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T10

1

T101

1

T243

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	55292	1			T7	3		T10	727		T17	168
write_address_byte	10196	1			T7	2		T10	115		T17	9
read_with_ack	2200	1			T10	34		T17	7		T54	6
read_with_nack	5573	1			T10	71		T17	3		T54	7
stop_byte	9291	1			T10	104		T17	5		T54	8
write_address_byte_nak	5355	1			T10	62		T17	8		T54	5
data_byte_nack	173615	1			T7	12		T10	2323		T17	542
stop_byte_nack	5697	1			T10	57		T17	5		T54	5
nakok_byte_nack	87304	1			T7	8		T10	1179		T17	284
nakok_addr_byte_nack	2741	1			T10	37		T17	5		T54	2