Unified Coverage Report :: Group :: tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	85.71	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_rd_wr_cg	85.71	1	100	1	64	64

---

Group Instance : i2c_rd_wr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance i2c_rd_wr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	24	4	20	83.33

Variables for Group Instance i2c_rd_wr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
address_match	2	0	2	100.00	100	1	1	2
cp_address_match	4	0	4	100.00	100	1	1	0
cp_read_byte	5	1	4	80.00	100	1	1	0
cp_write_byte	5	1	4	80.00	100	1	1	0
ip_mode_cp	2	0	2	100.00	100	1	1	0

Crosses for Group Instance i2c_rd_wr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_address_match_x_ip_mode	4	0	4	100.00	100	1	1	0
cross_write_byte_x_ip_mode	10	2	8	80.00	100	1	1	0
cross_read_byte_x_ip_mode	10	2	8	80.00	100	1	1	0

Summary for Variable address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for address_match

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11750460

1

T1

12232

T2

10245

T3

5127

auto[1]

16211298

1

T1

506

T2

493

T3

189

---

Summary for Variable cp_address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_address_match

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_addr_no_match	5842501	1			T1	5719		T2	4318		T3	1898
read_addr_match	11377634	1			T1	251		T2	240		T3	68
write_addr_no_match	5702820	1			T1	6497		T2	5915		T3	3211
write_addr_match	4755371	1			T1	249		T2	240		T3	115

---

Summary for Variable cp_read_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_read_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	3498772	1			T1	1187		T2	1087		T3	535
med	6666161	1			T1	2080		T2	1549		T3	648
low	6891817	1			T1	2647		T2	1887		T3	753
all_zero	163385	1			T1	56		T2	35		T3	30

---

Summary for Variable cp_write_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_write_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	2115863	1			T1	1436		T2	984		T3	994
med	4082781	1			T1	2623		T2	2524		T3	886
low	4160377	1			T1	2597		T2	2567		T3	1402
all_zero	99170	1			T1	90		T2	80		T3	44

---

Summary for Variable ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for ip_mode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

device

12485740

1

T1

12738

T2

10738

T3

5316

host

15476018

1

T7

2398

T10

223888

T17

35208

---

Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins

address_match

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

device

11750358

1

T1

12232

T2

10245

T3

5127

auto[0]

host

102

1

T145

2

T147

3

T204

3

auto[1]

device

735382

1

T1

506

T2

493

T3

189

auto[1]

host

15475916

1

T7

2398

T10

223888

T17

35208

---

Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	1225689	1			T1	1436		T2	984		T3	994
high	host	890174	1			T7	32		T10	11661		T17	2676
med	device	2364720	1			T1	2623		T2	2524		T3	886
med	host	1718061	1			T7	130		T10	22546		T17	5114
low	device	2432857	1			T1	2597		T2	2567		T3	1402
low	host	1727520	1			T7	140		T10	23491		T17	5565
all_zero	device	56264	1			T1	90		T2	80		T3	44
all_zero	host	42906	1			T7	11		T10	439		T17	109

---

Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	1225689	1			T1	1436		T2	984		T3	994
high	host	890174	1			T7	32		T10	11661		T17	2676
med	device	2364720	1			T1	2623		T2	2524		T3	886
med	host	1718061	1			T7	130		T10	22546		T17	5114
low	device	2432857	1			T1	2597		T2	2567		T3	1402
low	host	1727520	1			T7	140		T10	23491		T17	5565
all_zero	device	56264	1			T1	90		T2	80		T3	44
all_zero	host	42906	1			T7	11		T10	439		T17	109