Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35744621	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8319222

1

T1

239

T2

272

T3

125

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43227769	1			T1	10629		T2	597		T3	503
values[0x0]	417885	1			T1	126		T2	168		T3	66
values[0x1]	418189	1			T1	129		T2	124		T3	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25595572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18468271

1

T1

4837

T2

469

T3

298

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	164495	1			T1	32		T2	1		T3	3
valid_sources[0x01]	149885	1			T1	41		T2	2		T3	5
valid_sources[0x02]	160485	1			T1	52		T2	4		T3	1
valid_sources[0x03]	172195	1			T1	52		T3	2		T5	139
valid_sources[0x04]	153468	1			T1	33		T2	6		T3	1
valid_sources[0x05]	167974	1			T1	53		T3	4		T5	137
valid_sources[0x06]	150304	1			T1	40		T2	1		T3	3
valid_sources[0x07]	167830	1			T1	47		T2	1		T3	4
valid_sources[0x08]	156352	1			T1	39		T5	139		T6	123
valid_sources[0x09]	160797	1			T1	37		T2	1		T3	3
valid_sources[0x0a]	177290	1			T1	55		T2	3		T3	1
valid_sources[0x0b]	168110	1			T1	37		T2	2		T3	1
valid_sources[0x0c]	170370	1			T1	27		T2	3		T4	2
valid_sources[0x0d]	155478	1			T1	35		T2	3		T3	6
valid_sources[0x0e]	169422	1			T1	48		T2	7		T3	8
valid_sources[0x0f]	166871	1			T1	42		T2	3		T3	3
valid_sources[0x10]	156817	1			T1	48		T3	2		T4	3
valid_sources[0x11]	158334	1			T1	45		T2	3		T4	6
valid_sources[0x12]	164716	1			T1	38		T2	7		T3	3
valid_sources[0x13]	565967	1			T1	42		T2	3		T3	1
valid_sources[0x14]	158640	1			T1	44		T2	1		T3	3
valid_sources[0x15]	161219	1			T1	48		T2	3		T3	2
valid_sources[0x16]	164725	1			T1	47		T2	3		T3	1
valid_sources[0x17]	154435	1			T1	46		T2	5		T4	4
valid_sources[0x18]	162376	1			T1	52		T2	4		T3	2
valid_sources[0x19]	163147	1			T1	47		T3	5		T4	5
valid_sources[0x1a]	156777	1			T1	42		T3	1		T4	8
valid_sources[0x1b]	160293	1			T1	48		T2	8		T3	5
valid_sources[0x1c]	150604	1			T1	38		T2	1		T4	6
valid_sources[0x1d]	164466	1			T1	54		T2	4		T3	2
valid_sources[0x1e]	173035	1			T1	40		T2	7		T3	1
valid_sources[0x1f]	149758	1			T1	41		T2	12		T3	1
valid_sources[0x20]	163567	1			T1	31		T2	3		T3	2
valid_sources[0x21]	226092	1			T1	30		T2	4		T3	3
valid_sources[0x22]	187608	1			T1	33		T2	2		T5	152
valid_sources[0x23]	158931	1			T1	40		T2	2		T3	4
valid_sources[0x24]	155648	1			T1	44		T3	3		T4	1
valid_sources[0x25]	159896	1			T1	45		T2	9		T3	2
valid_sources[0x26]	155763	1			T1	47		T2	3		T4	8
valid_sources[0x27]	254952	1			T1	51		T2	2		T3	1
valid_sources[0x28]	164156	1			T1	50		T2	7		T3	4
valid_sources[0x29]	165868	1			T1	30		T2	3		T3	2
valid_sources[0x2a]	155063	1			T1	43		T3	3		T4	2
valid_sources[0x2b]	153483	1			T1	45		T2	4		T3	1
valid_sources[0x2c]	175018	1			T1	38		T2	1		T3	7
valid_sources[0x2d]	141116	1			T1	45		T3	4		T5	145
valid_sources[0x2e]	163119	1			T1	37		T2	11		T4	9
valid_sources[0x2f]	151868	1			T1	39		T2	6		T3	1
valid_sources[0x30]	172572	1			T1	44		T2	1		T4	5
valid_sources[0x31]	203445	1			T1	41		T2	6		T3	1
valid_sources[0x32]	178313	1			T1	54		T2	2		T3	2
valid_sources[0x33]	163200	1			T1	43		T2	5		T3	4
valid_sources[0x34]	158119	1			T1	26		T3	4		T4	9
valid_sources[0x35]	170911	1			T1	42		T3	8		T4	11
valid_sources[0x36]	151745	1			T1	38		T3	6		T4	7
valid_sources[0x37]	402606	1			T1	52		T3	1		T4	8
valid_sources[0x38]	188972	1			T1	37		T2	7		T3	3
valid_sources[0x39]	163329	1			T1	43		T2	1		T3	4
valid_sources[0x3a]	153389	1			T1	42		T2	1		T3	1
valid_sources[0x3b]	147254	1			T1	33		T2	12		T3	3
valid_sources[0x3c]	159626	1			T1	37		T3	4		T4	8
valid_sources[0x3d]	147413	1			T1	49		T2	15		T4	1
valid_sources[0x3e]	158608	1			T1	46		T2	6		T3	2
valid_sources[0x3f]	162007	1			T1	55		T2	4		T3	3
valid_sources[0x40]	144400	1			T1	42		T3	1		T4	22
valid_sources[0x41]	155915	1			T1	41		T2	20		T4	1
valid_sources[0x42]	160966	1			T1	35		T2	4		T4	7
valid_sources[0x43]	170676	1			T1	51		T2	6		T3	5
valid_sources[0x44]	181933	1			T1	53		T2	19		T3	3
valid_sources[0x45]	165159	1			T1	41		T2	3		T3	3
valid_sources[0x46]	154128	1			T1	37		T3	9		T4	6
valid_sources[0x47]	157636	1			T1	41		T2	3		T4	12
valid_sources[0x48]	150781	1			T1	43		T2	3		T3	1
valid_sources[0x49]	163780	1			T1	36		T2	2		T3	2
valid_sources[0x4a]	218894	1			T1	38		T3	7		T4	2
valid_sources[0x4b]	153061	1			T1	42		T3	1		T4	3
valid_sources[0x4c]	164369	1			T1	45		T3	2		T4	1
valid_sources[0x4d]	178310	1			T1	41		T3	2		T4	10
valid_sources[0x4e]	151618	1			T1	34		T2	3		T3	1
valid_sources[0x4f]	166217	1			T1	40		T2	4		T3	4
valid_sources[0x50]	153364	1			T1	46		T2	2		T3	4
valid_sources[0x51]	164478	1			T1	45		T2	2		T3	2
valid_sources[0x52]	155098	1			T1	47		T5	168		T6	92
valid_sources[0x53]	178276	1			T1	46		T2	7		T3	4
valid_sources[0x54]	191416	1			T1	40		T2	5		T3	1
valid_sources[0x55]	149373	1			T1	32		T2	6		T3	1
valid_sources[0x56]	155619	1			T1	43		T4	11		T5	147
valid_sources[0x57]	179328	1			T1	39		T2	7		T5	177
valid_sources[0x58]	153354	1			T1	36		T2	10		T3	2
valid_sources[0x59]	168333	1			T1	48		T2	1		T3	6
valid_sources[0x5a]	157127	1			T1	38		T3	2		T4	4
valid_sources[0x5b]	174812	1			T1	40		T2	1		T3	8
valid_sources[0x5c]	155266	1			T1	51		T2	11		T3	5
valid_sources[0x5d]	150592	1			T1	46		T2	4		T3	3
valid_sources[0x5e]	229445	1			T1	50		T2	2		T5	144
valid_sources[0x5f]	172712	1			T1	55		T2	6		T4	4
valid_sources[0x60]	172850	1			T1	41		T2	10		T3	7
valid_sources[0x61]	240809	1			T1	43		T2	6		T3	1
valid_sources[0x62]	162912	1			T1	44		T2	1		T3	4
valid_sources[0x63]	157930	1			T1	46		T2	14		T3	1
valid_sources[0x64]	160828	1			T1	44		T2	5		T3	5
valid_sources[0x65]	166257	1			T1	59		T2	1		T3	5
valid_sources[0x66]	165509	1			T1	42		T2	5		T3	6
valid_sources[0x67]	165429	1			T1	47		T2	2		T3	1
valid_sources[0x68]	185334	1			T1	33		T2	2		T3	4
valid_sources[0x69]	150531	1			T1	44		T2	4		T3	3
valid_sources[0x6a]	150157	1			T1	40		T2	3		T3	4
valid_sources[0x6b]	150102	1			T1	48		T3	2		T4	1
valid_sources[0x6c]	145634	1			T1	33		T2	5		T5	148
valid_sources[0x6d]	150548	1			T1	50		T2	6		T4	3
valid_sources[0x6e]	171119	1			T1	39		T2	9		T4	2
valid_sources[0x6f]	168677	1			T1	36		T2	11		T5	148
valid_sources[0x70]	141888	1			T1	49		T2	2		T3	2
valid_sources[0x71]	161647	1			T1	52		T2	4		T3	5
valid_sources[0x72]	151363	1			T1	44		T2	4		T4	2
valid_sources[0x73]	160272	1			T1	55		T2	1		T3	5
valid_sources[0x74]	201988	1			T1	50		T2	9		T4	3
valid_sources[0x75]	162108	1			T1	46		T2	1		T3	1
valid_sources[0x76]	159838	1			T1	44		T2	1		T3	3
valid_sources[0x77]	160308	1			T1	34		T2	2		T3	3
valid_sources[0x78]	165904	1			T1	38		T2	6		T3	1
valid_sources[0x79]	162855	1			T1	43		T2	9		T3	4
valid_sources[0x7a]	189676	1			T1	37		T2	3		T4	11
valid_sources[0x7b]	150935	1			T1	38		T2	5		T4	5
valid_sources[0x7c]	227724	1			T1	46		T2	2		T3	1
valid_sources[0x7d]	151334	1			T1	47		T2	2		T4	6
valid_sources[0x7e]	158523	1			T1	45		T2	1		T3	3
valid_sources[0x7f]	158039	1			T1	51		T2	13		T3	1
valid_sources[0x80]	172434	1			T1	33		T2	3		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7941325

1

T1

144

T2

127

T3

68

values[0x0]

all_enables

biggest_size

221195

1

T1

63

T2

95

T3

33

values[0x1]

all_enables

biggest_size

156702

1

T1

32

T2

50

T3

24