Module Definition
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Module : i2c_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 100.00 98.56 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.64 100.00 98.56 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 100.00 98.56 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.61 98.57 96.92 100.00 97.55 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.72 100.00 100.00 94.87 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_acq_fifo_next_data 66.67 66.67
u_acqdata_abyte 100.00 100.00
u_acqdata_signal 100.00 100.00
u_alert_test 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_controller_events_bus_timeout 88.89 100.00 66.67 100.00
u_controller_events_nack 100.00 100.00 100.00 100.00
u_controller_events_unhandled_nack_timeout 88.89 100.00 66.67 100.00
u_ctrl_ack_ctrl_en 100.00 100.00 100.00 100.00
u_ctrl_enablehost 100.00 100.00 100.00 100.00
u_ctrl_enabletarget 100.00 100.00 100.00 100.00
u_ctrl_llpbk 100.00 100.00 100.00 100.00
u_ctrl_multi_controller_monitor_en 100.00 100.00 100.00 100.00
u_ctrl_nack_addr_after_timeout 100.00 100.00 100.00 100.00
u_ctrl_tx_stretch_ctrl_en 100.00 100.00 100.00 100.00
u_fdata0_qe 100.00 100.00 100.00
u_fdata_fbyte 100.00 100.00 100.00 100.00
u_fdata_nakok 100.00 100.00 100.00 100.00
u_fdata_rcont 100.00 100.00 100.00 100.00
u_fdata_readb 100.00 100.00 100.00 100.00
u_fdata_start 100.00 100.00 100.00 100.00
u_fdata_stop 100.00 100.00 100.00 100.00
u_fifo_ctrl0_qe 100.00 100.00 100.00
u_fifo_ctrl_acqrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_fmtrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_rxrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_txrst 100.00 100.00 100.00 100.00
u_host_fifo_config0_qe 100.00 100.00 100.00
u_host_fifo_config_fmt_thresh 100.00 100.00 100.00 100.00
u_host_fifo_config_rx_thresh 100.00 100.00 100.00 100.00
u_host_fifo_status_fmtlvl 100.00 100.00
u_host_fifo_status_rxlvl 100.00 100.00
u_host_nack_handler_timeout_en 100.00 100.00 100.00 100.00
u_host_nack_handler_timeout_val 100.00 100.00 100.00 100.00
u_host_timeout_ctrl 100.00 100.00 100.00 100.00
u_intr_enable_acq_stretch 100.00 100.00 100.00 100.00
u_intr_enable_acq_threshold 100.00 100.00 100.00 100.00
u_intr_enable_cmd_complete 100.00 100.00 100.00 100.00
u_intr_enable_controller_halt 100.00 100.00 100.00 100.00
u_intr_enable_fmt_threshold 100.00 100.00 100.00 100.00
u_intr_enable_host_timeout 100.00 100.00 100.00 100.00
u_intr_enable_rx_overflow 100.00 100.00 100.00 100.00
u_intr_enable_rx_threshold 100.00 100.00 100.00 100.00
u_intr_enable_scl_interference 100.00 100.00 100.00 100.00
u_intr_enable_sda_interference 100.00 100.00 100.00 100.00
u_intr_enable_sda_unstable 100.00 100.00 100.00 100.00
u_intr_enable_stretch_timeout 100.00 100.00 100.00 100.00
u_intr_enable_tx_stretch 100.00 100.00 100.00 100.00
u_intr_enable_tx_threshold 100.00 100.00 100.00 100.00
u_intr_enable_unexp_stop 100.00 100.00 100.00 100.00
u_intr_state_acq_stretch 62.59 77.78 50.00 60.00
u_intr_state_acq_threshold 62.59 77.78 50.00 60.00
u_intr_state_cmd_complete 100.00 100.00 100.00 100.00
u_intr_state_controller_halt 62.59 77.78 50.00 60.00
u_intr_state_fmt_threshold 62.59 77.78 50.00 60.00
u_intr_state_host_timeout 100.00 100.00 100.00 100.00
u_intr_state_rx_overflow 100.00 100.00 100.00 100.00
u_intr_state_rx_threshold 62.59 77.78 50.00 60.00
u_intr_state_scl_interference 100.00 100.00 100.00 100.00
u_intr_state_sda_interference 100.00 100.00 100.00 100.00
u_intr_state_sda_unstable 100.00 100.00 100.00 100.00
u_intr_state_stretch_timeout 100.00 100.00 100.00 100.00
u_intr_state_tx_stretch 62.59 77.78 50.00 60.00
u_intr_state_tx_threshold 62.59 77.78 50.00 60.00
u_intr_state_unexp_stop 100.00 100.00 100.00 100.00
u_intr_test_acq_stretch 100.00 100.00
u_intr_test_acq_threshold 100.00 100.00
u_intr_test_cmd_complete 100.00 100.00
u_intr_test_controller_halt 100.00 100.00
u_intr_test_fmt_threshold 100.00 100.00
u_intr_test_host_timeout 100.00 100.00
u_intr_test_rx_overflow 100.00 100.00
u_intr_test_rx_threshold 100.00 100.00
u_intr_test_scl_interference 100.00 100.00
u_intr_test_sda_interference 100.00 100.00
u_intr_test_sda_unstable 100.00 100.00
u_intr_test_stretch_timeout 100.00 100.00
u_intr_test_tx_stretch 100.00 100.00
u_intr_test_tx_threshold 100.00 100.00
u_intr_test_unexp_stop 100.00 100.00
u_ovrd_sclval 100.00 100.00 100.00 100.00
u_ovrd_sdaval 100.00 100.00 100.00 100.00
u_ovrd_txovrden 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_rdata 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_status_ack_ctrl_stretch 100.00 100.00
u_status_acqempty 100.00 100.00
u_status_acqfull 100.00 100.00
u_status_fmtempty 100.00 100.00
u_status_fmtfull 100.00 100.00
u_status_hostidle 100.00 100.00
u_status_rxempty 100.00 100.00
u_status_rxfull 100.00 100.00
u_status_targetidle 100.00 100.00
u_status_txempty 100.00 100.00
u_status_txfull 100.00 100.00
u_target_ack_ctrl_nack 100.00 100.00
u_target_ack_ctrl_nbytes 100.00 100.00
u_target_events_bus_timeout 88.89 100.00 66.67 100.00
u_target_events_tx_pending 88.89 100.00 66.67 100.00
u_target_fifo_config0_qe 100.00 100.00 100.00
u_target_fifo_config_acq_thresh 100.00 100.00 100.00 100.00
u_target_fifo_config_tx_thresh 100.00 100.00 100.00 100.00
u_target_fifo_status_acqlvl 100.00 100.00
u_target_fifo_status_txlvl 100.00 100.00
u_target_id_address0 100.00 100.00 100.00 100.00
u_target_id_address1 100.00 100.00 100.00 100.00
u_target_id_mask0 100.00 100.00 100.00 100.00
u_target_id_mask1 100.00 100.00 100.00 100.00
u_target_nack_count 81.90 100.00 60.00 85.71
u_target_timeout_ctrl_en 100.00 100.00 100.00 100.00
u_target_timeout_ctrl_val 100.00 100.00 100.00 100.00
u_timeout_ctrl_en 100.00 100.00 100.00 100.00
u_timeout_ctrl_mode 100.00 100.00 100.00 100.00
u_timeout_ctrl_val 100.00 100.00 100.00 100.00
u_timing0_thigh 100.00 100.00 100.00 100.00
u_timing0_tlow 100.00 100.00 100.00 100.00
u_timing1_t_f 100.00 100.00 100.00 100.00
u_timing1_t_r 100.00 100.00 100.00 100.00
u_timing2_thd_sta 100.00 100.00 100.00 100.00
u_timing2_tsu_sta 100.00 100.00 100.00 100.00
u_timing3_thd_dat 100.00 100.00 100.00 100.00
u_timing3_tsu_dat 100.00 100.00 100.00 100.00
u_timing4_t_buf 100.00 100.00 100.00 100.00
u_timing4_tsu_sto 100.00 100.00 100.00 100.00
u_txdata 100.00 100.00 100.00 100.00
u_txdata0_qe 100.00 100.00 100.00
u_val_scl_rx 66.67 66.67
u_val_sda_rx 66.67 66.67


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_reg_top
Line No.TotalCoveredPercent
TOTAL365365100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN116411100.00
CONT_ASSIGN117911100.00
CONT_ASSIGN119511100.00
CONT_ASSIGN121111100.00
CONT_ASSIGN122711100.00
CONT_ASSIGN124311100.00
CONT_ASSIGN125911100.00
CONT_ASSIGN127511100.00
CONT_ASSIGN129111100.00
CONT_ASSIGN130711100.00
CONT_ASSIGN132311100.00
CONT_ASSIGN133911100.00
CONT_ASSIGN135511100.00
CONT_ASSIGN137111100.00
CONT_ASSIGN138711100.00
CONT_ASSIGN140311100.00
CONT_ASSIGN140911100.00
CONT_ASSIGN142311100.00
CONT_ASSIGN183811100.00
CONT_ASSIGN186611100.00
CONT_ASSIGN189411100.00
CONT_ASSIGN192211100.00
CONT_ASSIGN195011100.00
CONT_ASSIGN197811100.00
CONT_ASSIGN201911100.00
CONT_ASSIGN204711100.00
CONT_ASSIGN207511100.00
CONT_ASSIGN210311100.00
CONT_ASSIGN214411100.00
CONT_ASSIGN217211100.00
CONT_ASSIGN221311100.00
CONT_ASSIGN224111100.00
CONT_ASSIGN296511100.00
CONT_ASSIGN308311100.00
CONT_ASSIGN309811100.00
CONT_ASSIGN311411100.00
ALWAYS33313333100.00
CONT_ASSIGN336611100.00
ALWAYS337011100.00
CONT_ASSIGN340611100.00
CONT_ASSIGN340811100.00
CONT_ASSIGN341011100.00
CONT_ASSIGN341211100.00
CONT_ASSIGN341411100.00
CONT_ASSIGN341611100.00
CONT_ASSIGN341811100.00
CONT_ASSIGN342011100.00
CONT_ASSIGN342211100.00
CONT_ASSIGN342311100.00
CONT_ASSIGN342511100.00
CONT_ASSIGN342711100.00
CONT_ASSIGN342911100.00
CONT_ASSIGN343111100.00
CONT_ASSIGN343311100.00
CONT_ASSIGN343511100.00
CONT_ASSIGN343711100.00
CONT_ASSIGN343911100.00
CONT_ASSIGN344111100.00
CONT_ASSIGN344311100.00
CONT_ASSIGN344511100.00
CONT_ASSIGN344711100.00
CONT_ASSIGN344911100.00
CONT_ASSIGN345111100.00
CONT_ASSIGN345311100.00
CONT_ASSIGN345411100.00
CONT_ASSIGN345611100.00
CONT_ASSIGN345811100.00
CONT_ASSIGN346011100.00
CONT_ASSIGN346211100.00
CONT_ASSIGN346411100.00
CONT_ASSIGN346611100.00
CONT_ASSIGN346811100.00
CONT_ASSIGN347011100.00
CONT_ASSIGN347211100.00
CONT_ASSIGN347411100.00
CONT_ASSIGN347611100.00
CONT_ASSIGN347811100.00
CONT_ASSIGN348011100.00
CONT_ASSIGN348211100.00
CONT_ASSIGN348411100.00
CONT_ASSIGN348511100.00
CONT_ASSIGN348711100.00
CONT_ASSIGN348811100.00
CONT_ASSIGN349011100.00
CONT_ASSIGN349211100.00
CONT_ASSIGN349411100.00
CONT_ASSIGN349611100.00
CONT_ASSIGN349811100.00
CONT_ASSIGN350011100.00
CONT_ASSIGN350211100.00
CONT_ASSIGN350311100.00
CONT_ASSIGN350411100.00
CONT_ASSIGN350511100.00
CONT_ASSIGN350711100.00
CONT_ASSIGN350911100.00
CONT_ASSIGN351111100.00
CONT_ASSIGN351311100.00
CONT_ASSIGN351511100.00
CONT_ASSIGN351711100.00
CONT_ASSIGN351811100.00
CONT_ASSIGN352011100.00
CONT_ASSIGN352211100.00
CONT_ASSIGN352411100.00
CONT_ASSIGN352611100.00
CONT_ASSIGN352711100.00
CONT_ASSIGN352911100.00
CONT_ASSIGN353111100.00
CONT_ASSIGN353211100.00
CONT_ASSIGN353411100.00
CONT_ASSIGN353611100.00
CONT_ASSIGN353711100.00
CONT_ASSIGN353811100.00
CONT_ASSIGN353911100.00
CONT_ASSIGN354111100.00
CONT_ASSIGN354311100.00
CONT_ASSIGN354511100.00
CONT_ASSIGN354611100.00
CONT_ASSIGN354711100.00
CONT_ASSIGN354911100.00
CONT_ASSIGN355111100.00
CONT_ASSIGN355211100.00
CONT_ASSIGN355411100.00
CONT_ASSIGN355611100.00
CONT_ASSIGN355711100.00
CONT_ASSIGN355911100.00
CONT_ASSIGN356111100.00
CONT_ASSIGN356211100.00
CONT_ASSIGN356411100.00
CONT_ASSIGN356611100.00
CONT_ASSIGN356711100.00
CONT_ASSIGN356911100.00
CONT_ASSIGN357111100.00
CONT_ASSIGN357211100.00
CONT_ASSIGN357411100.00
CONT_ASSIGN357611100.00
CONT_ASSIGN357811100.00
CONT_ASSIGN357911100.00
CONT_ASSIGN358111100.00
CONT_ASSIGN358311100.00
CONT_ASSIGN358511100.00
CONT_ASSIGN358711100.00
CONT_ASSIGN358811100.00
CONT_ASSIGN358911100.00
CONT_ASSIGN359111100.00
CONT_ASSIGN359211100.00
CONT_ASSIGN359411100.00
CONT_ASSIGN359511100.00
CONT_ASSIGN359711100.00
CONT_ASSIGN359911100.00
CONT_ASSIGN360011100.00
CONT_ASSIGN360311100.00
CONT_ASSIGN360411100.00
CONT_ASSIGN360611100.00
CONT_ASSIGN360811100.00
CONT_ASSIGN360911100.00
CONT_ASSIGN361011100.00
CONT_ASSIGN361211100.00
CONT_ASSIGN361411100.00
CONT_ASSIGN361511100.00
CONT_ASSIGN361711100.00
CONT_ASSIGN361911100.00
CONT_ASSIGN362111100.00
CONT_ASSIGN362211100.00
CONT_ASSIGN362411100.00
CONT_ASSIGN362611100.00
ALWAYS36303333100.00
ALWAYS3667124124100.00
CONT_ASSIGN389800
CONT_ASSIGN390611100.00
CONT_ASSIGN390711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
1164 1 1
1179 1 1
1195 1 1
1211 1 1
1227 1 1
1243 1 1
1259 1 1
1275 1 1
1291 1 1
1307 1 1
1323 1 1
1339 1 1
1355 1 1
1371 1 1
1387 1 1
1403 1 1
1409 1 1
1423 1 1
1838 1 1
1866 1 1
1894 1 1
1922 1 1
1950 1 1
1978 1 1
2019 1 1
2047 1 1
2075 1 1
2103 1 1
2144 1 1
2172 1 1
2213 1 1
2241 1 1
2965 1 1
3083 1 1
3098 1 1
3114 1 1
3331 1 1
3332 1 1
3333 1 1
3334 1 1
3335 1 1
3336 1 1
3337 1 1
3338 1 1
3339 1 1
3340 1 1
3341 1 1
3342 1 1
3343 1 1
3344 1 1
3345 1 1
3346 1 1
3347 1 1
3348 1 1
3349 1 1
3350 1 1
3351 1 1
3352 1 1
3353 1 1
3354 1 1
3355 1 1
3356 1 1
3357 1 1
3358 1 1
3359 1 1
3360 1 1
3361 1 1
3362 1 1
3363 1 1
3366 1 1
3370 1 1
3406 1 1
3408 1 1
3410 1 1
3412 1 1
3414 1 1
3416 1 1
3418 1 1
3420 1 1
3422 1 1
3423 1 1
3425 1 1
3427 1 1
3429 1 1
3431 1 1
3433 1 1
3435 1 1
3437 1 1
3439 1 1
3441 1 1
3443 1 1
3445 1 1
3447 1 1
3449 1 1
3451 1 1
3453 1 1
3454 1 1
3456 1 1
3458 1 1
3460 1 1
3462 1 1
3464 1 1
3466 1 1
3468 1 1
3470 1 1
3472 1 1
3474 1 1
3476 1 1
3478 1 1
3480 1 1
3482 1 1
3484 1 1
3485 1 1
3487 1 1
3488 1 1
3490 1 1
3492 1 1
3494 1 1
3496 1 1
3498 1 1
3500 1 1
3502 1 1
3503 1 1
3504 1 1
3505 1 1
3507 1 1
3509 1 1
3511 1 1
3513 1 1
3515 1 1
3517 1 1
3518 1 1
3520 1 1
3522 1 1
3524 1 1
3526 1 1
3527 1 1
3529 1 1
3531 1 1
3532 1 1
3534 1 1
3536 1 1
3537 1 1
3538 1 1
3539 1 1
3541 1 1
3543 1 1
3545 1 1
3546 1 1
3547 1 1
3549 1 1
3551 1 1
3552 1 1
3554 1 1
3556 1 1
3557 1 1
3559 1 1
3561 1 1
3562 1 1
3564 1 1
3566 1 1
3567 1 1
3569 1 1
3571 1 1
3572 1 1
3574 1 1
3576 1 1
3578 1 1
3579 1 1
3581 1 1
3583 1 1
3585 1 1
3587 1 1
3588 1 1
3589 1 1
3591 1 1
3592 1 1
3594 1 1
3595 1 1
3597 1 1
3599 1 1
3600 1 1
3603 1 1
3604 1 1
3606 1 1
3608 1 1
3609 1 1
3610 1 1
3612 1 1
3614 1 1
3615 1 1
3617 1 1
3619 1 1
3621 1 1
3622 1 1
3624 1 1
3626 1 1
3630 1 1
3631 1 1
3632 1 1
3633 1 1
3634 1 1
3635 1 1
3636 1 1
3637 1 1
3638 1 1
3639 1 1
3640 1 1
3641 1 1
3642 1 1
3643 1 1
3644 1 1
3645 1 1
3646 1 1
3647 1 1
3648 1 1
3649 1 1
3650 1 1
3651 1 1
3652 1 1
3653 1 1
3654 1 1
3655 1 1
3656 1 1
3657 1 1
3658 1 1
3659 1 1
3660 1 1
3661 1 1
3662 1 1
3667 1 1
3668 1 1
3670 1 1
3671 1 1
3672 1 1
3673 1 1
3674 1 1
3675 1 1
3676 1 1
3677 1 1
3678 1 1
3679 1 1
3680 1 1
3681 1 1
3682 1 1
3683 1 1
3684 1 1
3688 1 1
3689 1 1
3690 1 1
3691 1 1
3692 1 1
3693 1 1
3694 1 1
3695 1 1
3696 1 1
3697 1 1
3698 1 1
3699 1 1
3700 1 1
3701 1 1
3702 1 1
3706 1 1
3707 1 1
3708 1 1
3709 1 1
3710 1 1
3711 1 1
3712 1 1
3713 1 1
3714 1 1
3715 1 1
3716 1 1
3717 1 1
3718 1 1
3719 1 1
3720 1 1
3724 1 1
3728 1 1
3729 1 1
3730 1 1
3731 1 1
3732 1 1
3733 1 1
3734 1 1
3738 1 1
3739 1 1
3740 1 1
3741 1 1
3742 1 1
3743 1 1
3744 1 1
3745 1 1
3746 1 1
3747 1 1
3748 1 1
3752 1 1
3756 1 1
3757 1 1
3758 1 1
3759 1 1
3760 1 1
3761 1 1
3765 1 1
3766 1 1
3767 1 1
3768 1 1
3772 1 1
3773 1 1
3777 1 1
3778 1 1
3782 1 1
3783 1 1
3787 1 1
3788 1 1
3792 1 1
3793 1 1
3794 1 1
3798 1 1
3799 1 1
3803 1 1
3804 1 1
3808 1 1
3809 1 1
3813 1 1
3814 1 1
3818 1 1
3819 1 1
3823 1 1
3824 1 1
3828 1 1
3829 1 1
3830 1 1
3834 1 1
3835 1 1
3836 1 1
3837 1 1
3841 1 1
3842 1 1
3846 1 1
3850 1 1
3854 1 1
3855 1 1
3859 1 1
3863 1 1
3864 1 1
3868 1 1
3872 1 1
3873 1 1
3877 1 1
3878 1 1
3879 1 1
3883 1 1
3884 1 1
3898 unreachable
3906 1 1
3907 1 1


Cond Coverage for Module : i2c_reg_top
TotalCoveredPercent
Conditions34734298.56
Logical34734298.56
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT168,T170,T171
10CoveredT145,T147,T174

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT168,T170,T171
010CoveredT145,T147,T174
100CoveredT168,T170,T171

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT145,T147,T174
010CoveredT87,T176,T177
100Not Covered

 LINE       3332
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3333
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3334
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3335
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3336
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3337
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3338
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       3339
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       3340
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3341
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3342
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3343
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3344
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3345
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3346
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3347
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3348
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3349
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3350
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3351
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3352
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3353
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3354
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3355
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3356
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3357
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_TIMEOUT_CTRL_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3358
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_NACK_COUNT_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3359
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ACK_CTRL_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       3360
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQ_FIFO_NEXT_DATA_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3361
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3362
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CONTROLLER_EVENTS_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       3363
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_EVENTS_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3366
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3366
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       3370
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT87,T176,T177

 LINE       3370
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b0111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
32 (addr_hit[31] & ((|(4'...CoveredT4,T5,T8
31 (addr_hit[30] & ((|(4'...CoveredT4,T5,T8
30 (addr_hit[29] & ((|(4'...CoveredT4,T5,T8
29 (addr_hit[28] & ((|(4'...CoveredT4,T5,T8
28 (addr_hit[27] & ((|(4'...CoveredT4,T5,T8
27 (addr_hit[26] & ((|(4'...CoveredT4,T5,T8
26 (addr_hit[25] & ((|(4'...CoveredT4,T5,T8
25 (addr_hit[24] & ((|(4'...CoveredT4,T5,T8
24 (addr_hit[23] & ((|(4'...CoveredT4,T5,T8
23 (addr_hit[22] & ((|(4'...CoveredT1,T2,T3
22 (addr_hit[21] & ((|(4'...CoveredT4,T5,T8
21 (addr_hit[20] & ((|(4'...CoveredT4,T5,T8
20 (addr_hit[19] & ((|(4'...CoveredT4,T5,T8
19 (addr_hit[18] & ((|(4'...CoveredT4,T5,T8
18 (addr_hit[17] & ((|(4'...CoveredT4,T5,T8
17 (addr_hit[16] & ((|(4'...CoveredT4,T5,T8
16 (addr_hit[15] & ((|(4'...CoveredT4,T5,T8
15 (addr_hit[14] & ((|(4'...CoveredT4,T5,T8
14 (addr_hit[13] & ((|(4'...CoveredT4,T5,T8
13 (addr_hit[12] & ((|(4'...CoveredT1,T2,T3
12 (addr_hit[11] & ((|(4'...CoveredT4,T5,T8
11 (addr_hit[10] & ((|(4'...CoveredT4,T5,T8
10 (addr_hit[9] & ((|(4'b...CoveredT4,T5,T8
9 (addr_hit[8] & ((|(4'b...CoveredT4,T5,T8
8 (addr_hit[7] & ((|(4'b...CoveredT4,T5,T8
7 (addr_hit[6] & ((|(4'b...CoveredT4,T5,T7
6 (addr_hit[5] & ((|(4'b...CoveredT1,T2,T3
5 (addr_hit[4] & ((|(4'b...CoveredT4,T5,T8
4 (addr_hit[3] & ((|(4'b...CoveredT4,T5,T8
3 (addr_hit[2] & ((|(4'b...CoveredT4,T5,T8
2 (addr_hit[1] & ((|(4'b...CoveredT4,T5,T8
1 (addr_hit[0] & ((|(4'b...CoveredT1,T2,T4

 LINE       3370
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       3370
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       3370
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11CoveredT4,T5,T7

 LINE       3370
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT1,T2,T3

 LINE       3370
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       3370
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T5
11CoveredT4,T5,T8

 LINE       3370
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT4,T5,T8

 LINE       3406
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT176,T177,T113
111CoveredT1,T2,T3

 LINE       3423
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT176,T177,T93
111CoveredT1,T2,T3

 LINE       3454
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT87,T176,T177
111CoveredT10,T98,T101

 LINE       3485
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT176,T177,T113
111CoveredT165,T166,T167

 LINE       3488
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT87,T176,T113
111CoveredT1,T2,T3

 LINE       3503
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT178
111CoveredT1,T2,T3

 LINE       3504
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T7
110CoveredT115,T179,T180
111CoveredT7,T10,T17

 LINE       3505
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T7
110CoveredT87,T176,T177
111CoveredT7,T10,T17

 LINE       3518
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT87,T176,T177
111CoveredT1,T2,T3

 LINE       3527
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT87,T176,T177
111CoveredT1,T2,T3

 LINE       3532
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT176,T113,T181
111CoveredT1,T2,T3

 LINE       3537
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT182,T93
111CoveredT10,T70,T86

 LINE       3538
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT147,T174,T183
111CoveredT1,T2,T3

 LINE       3539
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT176,T182,T96
111CoveredT41,T48,T42

 LINE       3546
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT174,T184,T185
111Not Covered

 LINE       3547
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT87,T176,T177
111CoveredT1,T2,T3

 LINE       3552
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT87,T176,T177
111CoveredT1,T2,T3

 LINE       3557
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT176,T177,T93
111CoveredT1,T2,T3

 LINE       3562
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT113,T186,T185
111CoveredT1,T2,T3

 LINE       3567
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT176,T177,T113
111CoveredT1,T2,T3

 LINE       3572
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT176,T177,T96
111CoveredT1,T2,T3

 LINE       3579
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT87,T176,T177
111CoveredT1,T2,T3

 LINE       3588
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT174,T93,T179
111CoveredT1,T2,T3

 LINE       3589
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT147,T176,T113
111CoveredT1,T2,T3

 LINE       3592
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT87,T176,T177
111CoveredT1,T2,T3

 LINE       3595
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT176,T113,T96
111CoveredT145,T146,T147

 LINE       3600
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110Not Covered
111CoveredT145,T146,T147

 LINE       3603
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT147,T182,T187
111CoveredT145,T146,T147

 LINE       3604
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT176,T93,T113
111CoveredT2,T3,T4

 LINE       3609
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT188,T189,T190
111Not Covered

 LINE       3610
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT176,T177,T113
111CoveredT74,T75,T76

 LINE       3615
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT176,T177,T118
111CoveredT3,T4,T5

 LINE       3622
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT176,T177,T113
111CoveredT145,T146,T147

Branch Coverage for Module : i2c_reg_top
Line No.TotalCoveredPercent
Branches 38 38 100.00
TERNARY 3366 2 2 100.00
IF 68 3 3 100.00
CASE 3668 33 33 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 3366 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T168,T170,T171
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 3668 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : i2c_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 391917721 44055302 0 0
reAfterRv 391917721 44055142 0 0
rePulse 391917721 43225712 0 0
wePulse 391917721 829430 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 391917721 44055302 0 0
T1 72640 10884 0 0
T2 77110 889 0 0
T3 39561 643 0 0
T4 162143 1378 0 0
T5 358951 38647 0 0
T6 130560 20272 0 0
T7 83038 40373 0 0
T8 112500 12009 0 0
T9 149501 1723 0 0
T10 252859 363511 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 391917721 44055142 0 0
T1 72640 10884 0 0
T2 77110 889 0 0
T3 39561 643 0 0
T4 162143 1378 0 0
T5 358951 38647 0 0
T6 130560 20272 0 0
T7 83038 40373 0 0
T8 112500 12009 0 0
T9 149501 1723 0 0
T10 252859 363511 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 391917721 43225712 0 0
T1 72640 10629 0 0
T2 77110 597 0 0
T3 39561 503 0 0
T4 162143 1235 0 0
T5 358951 38421 0 0
T6 130560 19889 0 0
T7 83038 40099 0 0
T8 112500 11907 0 0
T9 149501 1164 0 0
T10 252859 355269 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 391917721 829430 0 0
T1 72640 255 0 0
T2 77110 292 0 0
T3 39561 140 0 0
T4 162143 143 0 0
T5 358951 226 0 0
T6 130560 383 0 0
T7 83038 274 0 0
T8 112500 102 0 0
T9 149501 559 0 0
T10 252859 8242 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%