Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	391917721	0	0	0
ctrl_rd_A	391917721	1403	0	0
host_fifo_config_rd_A	391917721	7380	0	0
host_nack_handler_timeout_rd_A	391917721	1006	0	0
host_timeout_ctrl_rd_A	391917721	835	0	0
intr_enable_rd_A	391917721	3454	0	0
ovrd_rd_A	391917721	1875	0	0
target_fifo_config_rd_A	391917721	1032	0	0
target_id_rd_A	391917721	1205	0	0
target_timeout_ctrl_rd_A	391917721	920	0	0
timeout_ctrl_rd_A	391917721	1000	0	0
timing0_rd_A	391917721	968	0	0
timing1_rd_A	391917721	1006	0	0
timing2_rd_A	391917721	960	0	0
timing3_rd_A	391917721	915	0	0
timing4_rd_A	391917721	988	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	1403	0	0
T87	5805	3	0	0
T88	2133	8	0	0
T89	2992	26	0	0
T90	1460	1	0	0
T91	2008	30	0	0
T92	6657	90	0	0
T93	16322	285	0	0
T94	4650	21	0	0
T95	5810	52	0	0
T96	4728	15	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	7380	0	0
T42	2715	0	0	0
T48	1930	0	0	0
T52	176046	0	0	0
T97	300214	169	0	0
T98	0	112	0	0
T99	0	200	0	0
T100	0	81	0	0
T101	0	325	0	0
T102	0	159	0	0
T103	0	160	0	0
T104	0	177	0	0
T105	0	187	0	0
T106	0	644	0	0
T107	73436	0	0	0
T108	81825	0	0	0
T109	88009	0	0	0
T110	72060	0	0	0
T111	142587	0	0	0
T112	33522	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	1006	0	0
T87	5805	10	0	0
T88	2133	12	0	0
T89	2992	20	0	0
T90	1460	7	0	0
T91	2008	4	0	0
T92	6657	114	0	0
T93	16322	116	0	0
T94	4650	27	0	0
T113	6264	1	0	0
T114	1951	10	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	835	0	0
T87	5805	3	0	0
T89	2992	2	0	0
T92	6657	122	0	0
T93	16322	81	0	0
T94	4650	14	0	0
T95	5810	34	0	0
T115	8726	52	0	0
T116	1960	6	0	0
T117	2337	4	0	0
T118	9280	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	3454	0	0
T75	57779	0	0	0
T98	164139	27	0	0
T101	0	22	0	0
T119	0	13	0	0
T120	0	18	0	0
T121	0	8	0	0
T122	0	21	0	0
T123	0	25	0	0
T124	0	16	0	0
T125	0	10	0	0
T126	0	34	0	0
T127	82979	0	0	0
T128	124299	0	0	0
T129	115870	0	0	0
T130	227059	0	0	0
T131	45107	0	0	0
T132	1305	0	0	0
T133	130715	0	0	0
T134	45274	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	1875	0	0
T20	506839	0	0	0
T42	2715	48	0	0
T43	134826	0	0	0
T45	0	47	0	0
T51	13292	0	0	0
T80	11129	0	0	0
T81	8868	0	0	0
T112	33522	0	0	0
T132	0	47	0	0
T135	0	42	0	0
T136	0	51	0	0
T137	0	57	0	0
T138	0	54	0	0
T139	0	33	0	0
T140	0	50	0	0
T141	0	62	0	0
T142	2247	0	0	0
T143	185179	0	0	0
T144	179774	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	1032	0	0
T88	2133	2	0	0
T90	1460	7	0	0
T92	6657	120	0	0
T93	16322	126	0	0
T94	4650	10	0	0
T95	5810	67	0	0
T96	4728	7	0	0
T113	6264	5	0	0
T114	1951	5	0	0
T115	8726	43	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	1205	0	0
T87	5805	3	0	0
T88	2133	2	0	0
T91	2008	5	0	0
T92	6657	140	0	0
T93	16322	200	0	0
T94	4650	23	0	0
T95	5810	47	0	0
T96	4728	3	0	0
T114	1951	1	0	0
T115	8726	104	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	920	0	0
T87	5805	9	0	0
T88	2133	12	0	0
T89	2992	11	0	0
T90	1460	8	0	0
T91	2008	3	0	0
T92	6657	132	0	0
T93	16322	85	0	0
T94	4650	10	0	0
T95	5810	62	0	0
T96	4728	16	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	1000	0	0
T88	2133	7	0	0
T89	2992	14	0	0
T90	1460	4	0	0
T91	2008	6	0	0
T92	6657	119	0	0
T93	16322	115	0	0
T94	4650	28	0	0
T95	5810	21	0	0
T113	6264	21	0	0
T114	1951	4	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	968	0	0
T87	5805	3	0	0
T88	2133	19	0	0
T89	2992	41	0	0
T90	1460	10	0	0
T91	2008	7	0	0
T92	6657	115	0	0
T93	16322	120	0	0
T94	4650	22	0	0
T95	5810	20	0	0
T114	1951	5	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	1006	0	0
T87	5805	3	0	0
T89	2992	25	0	0
T90	1460	7	0	0
T92	6657	146	0	0
T93	16322	117	0	0
T94	4650	10	0	0
T95	5810	14	0	0
T96	4728	5	0	0
T113	6264	6	0	0
T114	1951	7	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	960	0	0
T88	2133	3	0	0
T89	2992	24	0	0
T90	1460	3	0	0
T91	2008	10	0	0
T92	6657	120	0	0
T93	16322	156	0	0
T94	4650	11	0	0
T95	5810	8	0	0
T113	6264	14	0	0
T114	1951	6	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	915	0	0
T87	5805	3	0	0
T88	2133	12	0	0
T90	1460	12	0	0
T91	2008	6	0	0
T92	6657	110	0	0
T93	16322	122	0	0
T94	4650	17	0	0
T95	5810	25	0	0
T113	6264	12	0	0
T114	1951	4	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391917721	988	0	0
T87	5805	7	0	0
T88	2133	8	0	0
T89	2992	5	0	0
T90	1460	6	0	0
T91	2008	6	0	0
T92	6657	129	0	0
T93	16322	100	0	0
T94	4650	52	0	0
T95	5810	36	0	0
T113	6264	9	0	0