Module Definition
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Module : i2c_target_fsm
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.72 87.46 73.33 81.11 76.69 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_i2c_target_fsm 83.72 87.46 73.33 81.11 76.69 100.00



Module Instance : tb.dut.i2c_core.u_i2c_target_fsm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.72 87.46 73.33 81.11 76.69 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.72 87.46 73.33 81.11 76.69 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.07 97.35 71.29 91.67 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_target_fsm
Line No.TotalCoveredPercent
TOTAL33529387.46
ALWAYS1278787.50
ALWAYS14133100.00
ALWAYS15166100.00
ALWAYS16255100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
ALWAYS17933100.00
ALWAYS18833100.00
ALWAYS19777100.00
CONT_ASSIGN20911100.00
ALWAYS21399100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23211100.00
ALWAYS23677100.00
ALWAYS24755100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN26811100.00
ALWAYS29944100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
CONT_ASSIGN32411100.00
ALWAYS32813011084.62
CONT_ASSIGN62411100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62911100.00
CONT_ASSIGN64311100.00
CONT_ASSIGN64811100.00
ALWAYS6521179682.05
ALWAYS98333100.00
ALWAYS99233100.00
CONT_ASSIGN99911100.00
CONT_ASSIGN100011100.00
CONT_ASSIGN100311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 0 1
135 1 1
136 1 1
MISSING_ELSE
141 1 1
142 1 1
144 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
162 1 1
163 1 1
164 1 1
166 1 1
168 1 1
172 1 1
173 1 1
174 1 1
175 1 1
179 1 1
180 1 1
182 1 1
188 1 1
189 1 1
191 1 1
197 1 1
198 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
209 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
220 2 2
221 1 1
223 1 1
228 1 1
230 1 1
232 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 2 2
MISSING_ELSE
MISSING_ELSE
247 1 1
248 1 1
249 1 1
250 2 2
MISSING_ELSE
MISSING_ELSE
264 1 1
267 1 1
268 1 1
299 1 1
300 1 1
301 1 1
302 1 1
MISSING_ELSE
316 1 1
320 1 1
324 1 1
328 1 1
329 1 1
330 1 1
331 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
342 1 1
343 1 1
344 1 1
345 1 1
347 1 1
352 1 1
353 1 1
354 1 1
355 1 1
356 1 1
357 1 1
366 1 1
367 1 1
368 1 1
372 1 1
373 1 1
375 1 1
376 1 1
377 1 1
378 1 1
MISSING_ELSE
MISSING_ELSE
384 1 1
386 1 1
389 0 1
MISSING_ELSE
394 1 1
395 1 1
399 1 1
400 1 1
404 1 1
405 1 1
408 1 1
409 1 1
413 1 1
415 1 1
416 1 1
MISSING_ELSE
419 1 1
420 1 1
422 1 1
==> MISSING_ELSE
428 1 1
432 1 1
433 1 1
437 1 1
440 1 1
444 1 1
447 1 1
451 1 1
454 1 1
455 1 1
457 1 1
MISSING_ELSE
462 1 1
463 1 1
464 1 1
468 1 1
472 1 1
473 1 1
476 0 1
MISSING_ELSE
481 1 1
482 1 1
486 1 1
487 1 1
491 1 1
492 1 1
494 1 1
495 1 1
496 1 1
497 1 1
==> MISSING_ELSE
503 0 1
504 0 1
505 0 1
507 0 1
508 0 1
512 0 1
513 0 1
==> MISSING_ELSE
519 0 1
520 0 1
521 0 1
526 1 1
527 1 1
528 1 1
530 1 1
531 0 1
535 0 1
536 0 1
537 1 1
538 1 1
539 1 1
540 1 1
542 1 1
MISSING_ELSE
548 1 1
549 1 1
550 1 1
552 1 1
556 0 1
MISSING_ELSE
561 1 1
562 1 1
563 1 1
567 1 1
568 1 1
569 1 1
570 1 1
573 1 1
574 0 1
575 0 1
576 0 1
MISSING_ELSE
582 1 1
583 1 1
584 1 1
605 1 1
606 1 1
607 1 1
612 1 1
613 1 1
614 0 1
616 1 1
618 1 1
619 1 1
620 1 1
MISSING_ELSE
624 1 1
625 1 1
629 1 1
643 1 1
648 1 1
652 1 1
653 1 1
654 1 1
655 1 1
656 1 1
658 1 1
670 1 1
671 1 1
672 1 1
MISSING_ELSE
679 1 1
680 1 1
681 1 1
683 1 1
684 1 1
687 1 1
MISSING_ELSE
693 1 1
695 0 1
696 1 1
697 1 1
699 1 1
701 0 1
708 0 1
709 0 1
712 0 1
716 0 1
==> MISSING_ELSE
723 2 2
MISSING_ELSE
727 1 1
728 1 1
729 1 1
730 1 1
MISSING_ELSE
735 1 1
741 1 1
747 0 1
748 1 1
754 1 1
755 1 1
757 1 1
760 1 1
==> MISSING_ELSE
766 1 1
767 1 1
769 1 1
774 2 2
MISSING_ELSE
778 1 1
779 1 1
780 1 1
781 1 1
MISSING_ELSE
786 1 1
787 1 1
788 1 1
790 1 1
791 1 1
792 1 1
==> MISSING_ELSE
798 1 1
799 1 1
MISSING_ELSE
805 1 1
807 1 1
808 1 1
811 1 1
MISSING_ELSE
819 1 1
823 1 1
824 1 1
825 1 1
826 1 1
MISSING_ELSE
831 1 1
833 0 1
834 1 1
835 1 1
836 0 1
837 1 1
841 1 1
843 1 1
==> MISSING_ELSE
849 2 2
MISSING_ELSE
853 1 1
854 1 1
855 1 1
856 1 1
MISSING_ELSE
861 1 1
862 1 1
==> MISSING_ELSE
870 0 1
871 0 1
872 0 1
873 0 1
874 0 1
875 0 1
==> MISSING_ELSE
881 0 1
882 0 1
==> MISSING_ELSE
890 1 1
891 0 1
892 1 1
898 1 1
MISSING_ELSE
904 1 1
905 1 1
906 0 1
907 1 1
914 1 1
915 1 1
916 1 1
919 1 1
MISSING_ELSE
924 1 1
925 1 1
MISSING_ELSE
936 1 1
937 0 1
938 1 1
939 1 1
940 1 1
941 1 1
MISSING_ELSE
947 1 1
948 1 1
MISSING_ELSE
964 1 1
973 0 1
974 1 1
975 1 1
976 1 1
977 1 1
MISSING_ELSE
983 1 1
984 1 1
986 1 1
992 1 1
993 1 1
995 1 1
999 1 1
1000 1 1
1003 1 1


Cond Coverage for Module : i2c_target_fsm
TotalCoveredPercent
Conditions1208873.33
Logical1208873.33
Non-Logical00
Event00

 LINE       155
 EXPRESSION (start_detect_i && target_idle_o)
             -------1------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (auto_ack_load_i && ack_ctrl_stretching)
             -------1-------    ---------2---------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11CoveredT2,T3,T4

 LINE       172
 EXPRESSION (((!ack_ctrl_mode_i)) || (auto_ack_cnt_q > '0))
             ----------1---------    ----------2----------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       209
 EXPRESSION (bit_idx == 4'd8)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       217
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       220
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       228
 EXPRESSION (((input_byte[7:1] & target_mask0_i) == target_address0_i) && (target_mask0_i != '0))
             ----------------------------1----------------------------    -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       228
 SUB-EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
                ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       228
 SUB-EXPRESSION (target_mask0_i != '0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION (((input_byte[7:1] & target_mask1_i) == target_address1_i) && (target_mask1_i != '0))
             ----------------------------1----------------------------    -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
                ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (target_mask1_i != '0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       232
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       240
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       249
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       301
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       320
 EXPRESSION (target_enable_i & xfer_for_us_q & rw_bit_q & stop_detect_i & ((!expect_stop)))
             -------1-------   ------2------   ----3---   ------4------   --------5-------
-1--2--3--4--5-StatusTests
01111Not Covered
10111CoveredT11,T12,T13
11011CoveredT1,T2,T3
11101CoveredT1,T2,T3
11110CoveredT1,T2,T3
11111CoveredT14,T15,T16

 LINE       324
 EXPRESSION (((!nack_transaction_q)) && nack_transaction_d)
             -----------1-----------    ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       408
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       494
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       573
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

 LINE       573
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11Not Covered

 LINE       605
 EXPRESSION (target_enable_i && (stop_detect_i || bus_timeout_i))
             -------1-------    ----------------2---------------
-1--2-StatusTests
01CoveredT7,T10,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       605
 SUB-EXPRESSION (stop_detect_i || bus_timeout_i)
                 ------1------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       607
 EXPRESSION (bus_timeout_i && rw_bit_q)
             ------1------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       613
 EXPRESSION (nack_transaction_q || bus_timeout_i)
             ---------1--------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       618
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT7,T10,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       624
 EXPRESSION (((!acq_fifo_plenty_space)) || ((!can_auto_ack)))
             -------------1------------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT18,T19,T20

 LINE       629
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       643
 EXPRESSION (((!tx_fifo_rvalid_i)) || unhandled_tx_stretch_event_i || (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------    --------------2-------------    --------------3--------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010Not Covered
100CoveredT1,T2,T3

 LINE       696
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       735
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       786
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       834
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       861
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       881
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       898
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---
-1-StatusTests
0CoveredT18,T19,T20
1Not Covered

 LINE       924
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT2,T3,T5
1CoveredT2,T3,T5

 LINE       936
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

 LINE       936
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11Not Covered

 LINE       947
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT2,T3,T4

 LINE       964
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       974
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT7,T10,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       976
 EXPRESSION (stop_detect_i || bus_timeout_i)
             ------1------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

FSM Coverage for Module : i2c_target_fsm
Summary for FSM :: state_q
TotalCoveredPercent
States 26 24 92.31 (Not included in score)
Transitions 90 73 81.11
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AcquireAckHold 854 Covered T1,T2,T3
AcquireAckPulse 849 Covered T1,T2,T3
AcquireAckSetup 843 Covered T1,T2,T3
AcquireAckWait 824 Covered T1,T2,T3
AcquireByte 760 Covered T1,T2,T3
AcquireStart 975 Covered T1,T2,T3
AddrAckHold 728 Covered T1,T2,T3
AddrAckPulse 723 Covered T1,T2,T3
AddrAckSetup 699 Covered T1,T2,T3
AddrAckWait 681 Covered T1,T2,T3
AddrRead 671 Covered T1,T2,T3
Idle 973 Covered T1,T2,T3
StretchAcqFull 841 Covered T2,T3,T4
StretchAcqSetup 939 Covered T2,T3,T4
StretchAddr 754 Covered T18,T19,T20
StretchAddrAck 712 Not Covered
StretchAddrAckSetup 873 Not Covered
StretchTx 767 Covered T2,T3,T5
StretchTxSetup 914 Covered T2,T3,T5
TransmitAck 788 Covered T1,T2,T3
TransmitAckPulse 799 Covered T1,T2,T3
TransmitHold 779 Covered T1,T2,T3
TransmitPulse 774 Covered T1,T2,T3
TransmitSetup 769 Covered T1,T2,T3
TransmitWait 757 Covered T1,T2,T3
WaitForStop 687 Covered T1,T2,T3


transitionsLine No.CoveredTests
AcquireAckHold->AcquireByte 862 Covered T1,T2,T3
AcquireAckHold->AcquireStart 975 Covered T15,T21
AcquireAckHold->Idle 973 Covered T15,T21
AcquireAckPulse->AcquireAckHold 854 Covered T1,T2,T3
AcquireAckPulse->AcquireStart 975 Covered T15,T21
AcquireAckPulse->Idle 973 Covered T15,T21
AcquireAckSetup->AcquireAckPulse 849 Covered T1,T2,T3
AcquireAckSetup->AcquireStart 975 Covered T15,T21
AcquireAckSetup->Idle 973 Covered T15,T21
AcquireAckWait->AcquireAckSetup 843 Covered T1,T2,T3
AcquireAckWait->AcquireStart 975 Covered T15,T21
AcquireAckWait->Idle 973 Covered T15,T21
AcquireAckWait->StretchAcqFull 841 Covered T2,T3,T4
AcquireAckWait->WaitForStop 833 Not Covered
AcquireByte->AcquireAckWait 824 Covered T1,T2,T3
AcquireByte->AcquireStart 975 Covered T1,T2,T3
AcquireByte->Idle 973 Covered T1,T2,T3
AcquireStart->AddrRead 671 Covered T1,T2,T3
AcquireStart->Idle 973 Covered T15,T21
AddrAckHold->AcquireByte 760 Covered T1,T2,T3
AddrAckHold->AcquireStart 975 Covered T15,T21
AddrAckHold->Idle 973 Covered T15,T21
AddrAckHold->StretchAddr 754 Covered T18,T19,T20
AddrAckHold->TransmitWait 757 Covered T1,T2,T3
AddrAckHold->WaitForStop 747 Not Covered
AddrAckPulse->AcquireStart 975 Covered T15,T21
AddrAckPulse->AddrAckHold 728 Covered T1,T2,T3
AddrAckPulse->Idle 973 Covered T15,T21
AddrAckSetup->AcquireStart 975 Covered T15,T21
AddrAckSetup->AddrAckPulse 723 Covered T1,T2,T3
AddrAckSetup->Idle 973 Covered T15,T21
AddrAckWait->AcquireStart 975 Covered T15,T21
AddrAckWait->AddrAckSetup 699 Covered T1,T2,T3
AddrAckWait->Idle 973 Covered T15,T21
AddrAckWait->StretchAddrAck 712 Not Covered
AddrAckWait->WaitForStop 695 Not Covered
AddrRead->AcquireStart 975 Covered T22,T23,T24
AddrRead->AddrAckWait 681 Covered T1,T2,T3
AddrRead->Idle 973 Covered T25,T26,T27
AddrRead->WaitForStop 687 Covered T28,T29,T30
Idle->AcquireStart 975 Covered T1,T2,T3
StretchAcqFull->AcquireStart 975 Covered T15,T21
StretchAcqFull->Idle 973 Covered T15,T21
StretchAcqFull->StretchAcqSetup 939 Covered T2,T3,T4
StretchAcqFull->WaitForStop 937 Not Covered
StretchAcqSetup->AcquireAckSetup 948 Covered T2,T3,T4
StretchAcqSetup->AcquireStart 975 Not Covered
StretchAcqSetup->Idle 973 Not Covered
StretchAddr->AcquireByte 898 Covered T18,T19,T20
StretchAddr->AcquireStart 975 Covered T15,T21
StretchAddr->Idle 973 Covered T15,T21
StretchAddr->StretchTx 898 Not Covered
StretchAddr->WaitForStop 891 Not Covered
StretchAddrAck->AcquireStart 975 Not Covered
StretchAddrAck->Idle 973 Not Covered
StretchAddrAck->StretchAddrAckSetup 873 Not Covered
StretchAddrAck->WaitForStop 871 Not Covered
StretchAddrAckSetup->AcquireStart 975 Not Covered
StretchAddrAckSetup->AddrAckSetup 882 Not Covered
StretchAddrAckSetup->Idle 973 Not Covered
StretchTx->AcquireStart 975 Covered T15,T21
StretchTx->Idle 973 Covered T15,T21
StretchTx->StretchTxSetup 914 Covered T2,T3,T5
StretchTx->WaitForStop 906 Not Covered
StretchTxSetup->AcquireStart 975 Covered T15,T21
StretchTxSetup->Idle 973 Covered T15,T21
StretchTxSetup->TransmitSetup 925 Covered T2,T3,T5
TransmitAck->AcquireStart 975 Covered T15,T21
TransmitAck->Idle 973 Covered T15,T21
TransmitAck->TransmitAckPulse 799 Covered T1,T2,T3
TransmitAckPulse->AcquireStart 975 Covered T15,T21
TransmitAckPulse->Idle 973 Covered T15,T21
TransmitAckPulse->TransmitWait 808 Covered T1,T2,T3
TransmitAckPulse->WaitForStop 811 Covered T1,T2,T3
TransmitHold->AcquireStart 975 Covered T15,T21
TransmitHold->Idle 973 Covered T15,T21
TransmitHold->TransmitAck 788 Covered T1,T2,T3
TransmitHold->TransmitSetup 792 Covered T1,T2,T3
TransmitPulse->AcquireStart 975 Covered T14,T15,T16
TransmitPulse->Idle 973 Covered T14,T15,T16
TransmitPulse->TransmitHold 779 Covered T1,T2,T3
TransmitSetup->AcquireStart 975 Covered T15,T21
TransmitSetup->Idle 973 Covered T15,T21
TransmitSetup->TransmitPulse 774 Covered T1,T2,T3
TransmitWait->AcquireStart 975 Covered T15,T21
TransmitWait->Idle 973 Covered T15,T21
TransmitWait->StretchTx 767 Covered T2,T3,T5
TransmitWait->TransmitSetup 769 Covered T1,T2,T3
WaitForStop->AcquireStart 975 Covered T1,T2,T3
WaitForStop->Idle 973 Covered T1,T2,T3



Branch Coverage for Module : i2c_target_fsm
Line No.TotalCoveredPercent
Branches 163 125 76.69
IF 128 6 4 66.67
IF 141 2 2 100.00
IF 151 4 4 100.00
IF 162 3 3 100.00
IF 179 2 2 100.00
IF 188 2 2 100.00
IF 197 2 2 100.00
IF 213 5 5 100.00
IF 236 5 5 100.00
IF 247 4 4 100.00
IF 299 3 3 100.00
CASE 347 44 32 72.73
IF 605 4 3 75.00
CASE 658 69 47 68.12
IF 964 4 3 75.00
IF 983 2 2 100.00
IF 992 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 128 if (load_tcount) -2-: 129 case (tcount_sel) -3-: 135 if (target_enable_i)

Branches:
-1--2--3-StatusTests
1 tSetupData - Covered T2,T3,T4
1 tHoldData - Covered T1,T2,T3
1 tNoDelay - Not Covered
1 default - Not Covered
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (actively_stretching) -3-: 155 if ((start_detect_i && target_idle_o))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 162 if ((!rst_ni)) -2-: 164 if ((auto_ack_load_i && ack_ctrl_stretching))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 179 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 188 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 197 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 213 if ((!rst_ni)) -2-: 215 if (start_detect_i) -3-: 217 if ((scl_i_q && (!scl_i))) -4-: 220 if ((input_byte_clr || bit_ack))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 236 if ((!rst_ni)) -2-: 238 if (input_byte_clr) -3-: 240 if (((!scl_i_q) && scl_i)) -4-: 241 if ((!bit_ack))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 247 if ((!rst_ni)) -2-: 249 if (((!scl_i_q) && scl_i)) -3-: 250 if (bit_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T3
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 299 if ((!rst_ni)) -2-: 301 if ((bit_ack && address_match))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 347 case (state_q) -2-: 375 if (bit_ack) -3-: 376 if (address_match) -4-: 386 if (scl_i) -5-: 408 if ((tcount_q == 16'b1)) -6-: 409 if (nack_transaction_q) -7-: 413 if ((!stretch_addr)) -8-: 419 if (restart_det_q) -9-: 455 if ((!scl_i)) -10-: 473 if (scl_i) -11-: 494 if ((tcount_q == 16'b1)) -12-: 507 if (nack_timeout) -13-: 530 if (nack_timeout) -14-: 537 if ((!stretch_addr)) -15-: 539 if (restart_det_q) -16-: 552 if (nack_timeout) -17-: 573 if ((nack_timeout || (sw_nack_i && (!can_auto_ack))))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTests
Idle - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireStart - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrRead 1 1 - - - - - - - - - - - - - - Covered T1,T2,T3
AddrRead 1 0 - - - - - - - - - - - - - - Covered T28,T29,T30
AddrRead 0 - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckWait - - 1 - - - - - - - - - - - - - Not Covered
AddrAckWait - - 0 - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckSetup - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckPulse - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckHold - - - 1 1 - - - - - - - - - - - Not Covered
AddrAckHold - - - 1 0 1 - - - - - - - - - - Covered T1,T2,T3
AddrAckHold - - - 1 0 0 - - - - - - - - - - Covered T18,T19,T20
AddrAckHold - - - 1 - - 1 - - - - - - - - - Covered T1,T2,T3
AddrAckHold - - - 1 - - 0 - - - - - - - - - Covered T1,T2,T3
AddrAckHold - - - 0 - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitSetup - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitPulse - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitHold - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitAck - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitAckPulse - - - - - - - 1 - - - - - - - - Covered T1,T2,T3
TransmitAckPulse - - - - - - - 0 - - - - - - - - Covered T1,T2,T3
WaitForStop - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireByte - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckWait - - - - - - - - 1 - - - - - - - Not Covered
AcquireAckWait - - - - - - - - 0 - - - - - - - Covered T1,T2,T3
AcquireAckSetup - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckPulse - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckHold - - - - - - - - - 1 - - - - - - Covered T1,T2,T3
AcquireAckHold - - - - - - - - - 0 - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - 1 - - - - - Not Covered
StretchAddrAck - - - - - - - - - - 0 - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - 1 - - - - Not Covered
StretchAddr - - - - - - - - - - - 0 1 1 - - Covered T18,T19,T20
StretchAddr - - - - - - - - - - - 0 1 0 - - Covered T18,T19,T20
StretchAddr - - - - - - - - - - - 0 0 - - - Covered T18,T19,T20
StretchTx - - - - - - - - - - - - - - 1 - Not Covered
StretchTx - - - - - - - - - - - - - - 0 - Covered T2,T3,T5
StretchTxSetup - - - - - - - - - - - - - - - - Covered T2,T3,T5
StretchAcqFull - - - - - - - - - - - - - - - 1 Not Covered
StretchAcqFull - - - - - - - - - - - - - - - 0 Covered T2,T3,T4
StretchAcqSetup - - - - - - - - - - - - - - - - Covered T2,T3,T4
default - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 605 if ((target_enable_i && (stop_detect_i || bus_timeout_i))) -2-: 613 if ((nack_transaction_q || bus_timeout_i)) -3-: 618 if ((target_enable_i && start_detect_i))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 658 case (state_q) -2-: 670 if ((!scl_i)) -3-: 679 if (bit_ack) -4-: 680 if (address_match) -5-: 693 if (scl_i) -6-: 696 if ((tcount_q == 16'b1)) -7-: 697 if ((!nack_addr_after_timeout_i)) -8-: 701 if (nack_transaction_q) -9-: 709 if (stretch_addr) -10-: 723 if (scl_i) -11-: 727 if ((!scl_i)) -12-: 735 if ((tcount_q == 16'b1)) -13-: 741 if (nack_transaction_q) -14-: 748 if (stretch_addr) -15-: 755 if (rw_bit_q) -16-: 766 if (stretch_tx) -17-: 774 if (scl_i) -18-: 778 if ((!scl_i)) -19-: 786 if ((tcount_q == 16'b1)) -20-: 787 if (bit_ack) -21-: 798 if (scl_i) -22-: 805 if ((!scl_i)) -23-: 807 if (host_ack) -24-: 823 if (bit_ack) -25-: 831 if (scl_i) -26-: 834 if ((tcount_q == 16'b1)) -27-: 835 if (nack_transaction_q) -28-: 837 if (stretch_rx) -29-: 849 if (scl_i) -30-: 853 if ((!scl_i)) -31-: 861 if ((tcount_q == 16'b1)) -32-: 870 if (nack_timeout) -33-: 872 if ((!stretch_addr)) -34-: 881 if ((tcount_q == 16'b1)) -35-: 890 if (nack_timeout) -36-: 892 if ((!stretch_addr)) -37-: 898 (rw_bit_q) ? -38-: 905 if (nack_timeout) -39-: 907 if ((!stretch_tx)) -40-: 924 if ((tcount_q == 16'b1)) -41-: 936 if ((nack_timeout || (sw_nack_i && (!can_auto_ack)))) -42-: 938 if ((~stretch_rx)) -43-: 947 if ((tcount_q == 16'b1))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40--41--42--43-StatusTests
Idle - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireStart 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireStart 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrRead - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrRead - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T28,T29,T30
AddrRead - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckWait - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckWait - - - 0 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckSetup - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckSetup - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckPulse - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckPulse - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckHold - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - - - - - - - - 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T18,T19,T20
AddrAckHold - - - - - - - - - - 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckHold - - - - - - - - - - 1 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AddrAckHold - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T3,T5
TransmitWait - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitSetup - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitSetup - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitPulse - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitPulse - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitHold - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitHold - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitHold - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitAck - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitAck - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
WaitForStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireByte - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireByte - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 1 - - - - - - - - - - - - - - - Covered T2,T3,T4
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 0 - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - - - - - - - - Not Covered
AcquireAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckPulse - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckPulse - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckHold - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - Covered T1,T2,T3
AcquireAckHold - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 - - - - - - Covered T18,T19,T20
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - Covered T18,T19,T20
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - Not Covered
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - Covered T2,T3,T5
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - Covered T2,T3,T5
StretchTxSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - Covered T2,T3,T5
StretchTxSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Covered T2,T3,T5
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - Not Covered
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - Covered T2,T3,T4
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - Covered T2,T3,T4
StretchAcqSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T2,T3,T4
StretchAcqSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T2,T3,T4
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 964 if (((!target_idle) && (!target_enable_i))) -2-: 974 if ((target_enable_i && start_detect_i)) -3-: 976 if ((stop_detect_i || bus_timeout_i))

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 983 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 992 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : i2c_target_fsm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AcqDepthRdCheck_A 391292202 3530068 0 0
AcqFifoDeepEnough_A 391292202 391124003 0 0
SclOutputGlitch_A 391292202 57328 0 0


AcqDepthRdCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391292202 3530068 0 0
T1 72640 308 0 0
T2 77110 1060 0 0
T3 39561 97 0 0
T4 162143 0 0 0
T5 358951 20963 0 0
T6 130560 606 0 0
T7 83038 0 0 0
T8 112500 3458 0 0
T9 149501 453 0 0
T10 252859 0 0 0
T28 0 127 0 0
T31 0 36393 0 0
T32 0 9249 0 0

AcqFifoDeepEnough_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391292202 391124003 0 0
T1 72640 72554 0 0
T2 77110 77050 0 0
T3 39561 39489 0 0
T4 162143 162136 0 0
T5 358951 358857 0 0
T6 130560 130491 0 0
T7 83038 82968 0 0
T8 112500 112445 0 0
T9 149501 149429 0 0
T10 252859 252829 0 0

SclOutputGlitch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391292202 57328 0 0
T2 77110 52 0 0
T3 39561 24 0 0
T4 162143 69 0 0
T5 358951 111 0 0
T6 130560 0 0 0
T7 83038 0 0 0
T8 112500 41 0 0
T9 149501 49 0 0
T10 252859 0 0 0
T18 938277 454 0 0
T28 0 50 0 0
T31 0 169 0 0
T32 0 45 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%