Group : i2c_env_pkg::i2c_scl_stretch_cg
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Group : i2c_env_pkg::i2c_scl_stretch_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
40.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv



Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 3 3 50.00
Crosses 4 3 1 25.00


Variables for Group i2c_env_pkg::i2c_scl_stretch_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_fifo_size 2 1 1 50.00 100 1 1 0
cp_host_mode_stretch 1 1 0 0.00 100 1 1 0
cp_target_scl_stretch_addr_write 1 1 0 0.00 100 1 1 0
cp_tx_fifo_size 2 0 2 100.00 100 1 1 0


Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_target_scl_stretch_read 4 3 1 25.00 100 1 1 0


Summary for Variable cp_acq_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_acq_fifo_size

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
not_empty 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
empty 10120 1 T1 157 T12 55 T7 607



Summary for Variable cp_host_mode_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_host_mode_stretch

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
stretch 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded



Summary for Variable cp_target_scl_stretch_addr_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_target_scl_stretch_addr_write

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
addr_write_byte_stretch 0 1 1



Summary for Variable cp_tx_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_tx_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 26 1 T59 26 - - - -
empty 10094 1 T1 157 T12 55 T7 607



Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 3 1 25.00 1
Automatically Generated Cross Bins 2 1 1 50.00 1
User Defined Cross Bins 2 2 0 0.00


Automatically Generated Cross Bins for cp_target_scl_stretch_read

Uncovered bins
cp_acq_fifo_sizecp_tx_fifo_sizeCOUNTAT LEASTNUMBERSTATUS
[empty] [not_empty] 0 1 1


Covered bins
cp_acq_fifo_sizecp_tx_fifo_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
empty empty 1528 1 T1 65 T12 33 T7 9


User Defined Cross Bins for cp_target_scl_stretch_read

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_byte_stretch 0 1 1
scl_stretch_read_request 0 1 1

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