Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
52.74 40.66 40.72 91.14 0.00 42.98 99.68 54.00


Total tests in report: 161
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
43.35 43.35 39.43 39.43 36.66 36.66 84.79 84.79 0.00 0.00 41.77 41.77 91.08 91.08 9.68 9.68 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.164798991
49.24 5.89 40.62 1.19 39.07 2.41 93.39 8.60 0.00 0.00 42.91 1.13 92.04 0.96 36.63 26.95 /workspace/coverage/cover_reg_top/36.i2c_intr_test.147010016
51.77 2.54 40.66 0.03 39.44 0.38 97.26 3.87 0.00 0.00 42.98 0.07 96.82 4.78 45.26 8.63 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3447620611
52.40 0.62 40.66 0.00 39.44 0.00 97.51 0.25 0.00 0.00 42.98 0.00 96.82 0.00 49.37 4.11 /workspace/coverage/cover_reg_top/29.i2c_intr_test.1626691378
52.80 0.41 40.66 0.00 39.44 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 2.87 49.37 0.00 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1124075965
53.08 0.27 40.66 0.00 40.20 0.75 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 50.53 1.16 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2644823004
53.24 0.17 40.66 0.00 40.20 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 51.68 1.16 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2146296432
53.32 0.08 40.66 0.00 40.20 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 52.21 0.53 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2616836915
53.38 0.06 40.66 0.00 40.20 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 52.63 0.42 /workspace/coverage/cover_reg_top/17.i2c_intr_test.426659229
53.44 0.06 40.66 0.00 40.38 0.19 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 52.84 0.21 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2565430011
53.48 0.05 40.66 0.00 40.38 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.16 0.32 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2544251219
53.53 0.05 40.66 0.00 40.38 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.47 0.32 /workspace/coverage/cover_reg_top/27.i2c_intr_test.183307586
53.56 0.03 40.66 0.00 40.50 0.11 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.58 0.11 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2639401551
53.57 0.02 40.66 0.00 40.50 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.68 0.11 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3425981245
53.59 0.02 40.66 0.00 40.50 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.79 0.11 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.781861468
53.60 0.02 40.66 0.00 40.50 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.89 0.11 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.29849232
53.62 0.02 40.66 0.00 40.50 0.00 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.00 0.11 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2484928297
53.63 0.01 40.66 0.00 40.57 0.08 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.00 0.00 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2874569419
53.64 0.01 40.66 0.00 40.65 0.08 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.00 0.00 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3768588058
53.64 0.01 40.66 0.00 40.68 0.04 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.00 0.00 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2394864619
53.65 0.01 40.66 0.00 40.72 0.04 97.51 0.00 0.00 0.00 42.98 0.00 99.68 0.00 54.00 0.00 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1579726097

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3664474784
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.17691361
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1436619842
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3148596909
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.1409916172
/workspace/coverage/cover_reg_top/0.i2c_intr_test.3235773044
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.1064542537
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3994455014
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2948435338
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3527237617
/workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.200743756
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1329933975
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.1334190555
/workspace/coverage/cover_reg_top/1.i2c_intr_test.397575802
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1962878504
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.2543067144
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3229267096
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.1174451544
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1131977463
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.2364320166
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3868849994
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.910117120
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.2220425031
/workspace/coverage/cover_reg_top/11.i2c_intr_test.1938120889
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1167749529
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.105728558
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.1406831453
/workspace/coverage/cover_reg_top/12.i2c_intr_test.365221253
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.4052195832
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2773565003
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3118680448
/workspace/coverage/cover_reg_top/13.i2c_intr_test.2315987818
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1608974468
/workspace/coverage/cover_reg_top/13.i2c_tl_errors.3833013883
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2135685270
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.198043041
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.2810031475
/workspace/coverage/cover_reg_top/14.i2c_intr_test.1816931473
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3048606081
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.138510680
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3726132939
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3012689021
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1035355042
/workspace/coverage/cover_reg_top/15.i2c_intr_test.1005875909
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.641578118
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4044761670
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2221750937
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.1982719725
/workspace/coverage/cover_reg_top/16.i2c_intr_test.283380133
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2390225735
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.4268365572
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3111723105
/workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2489203568
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.3600137876
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2698909295
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.679413364
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2791391382
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.673881592
/workspace/coverage/cover_reg_top/18.i2c_intr_test.2733237665
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2030483069
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.3714526965
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3729288451
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.1817824609
/workspace/coverage/cover_reg_top/19.i2c_intr_test.1054207717
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3621158845
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.4221705748
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1681313927
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2037026364
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2749003902
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.421329821
/workspace/coverage/cover_reg_top/2.i2c_intr_test.851400107
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2726215782
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.1175250252
/workspace/coverage/cover_reg_top/20.i2c_intr_test.2460529308
/workspace/coverage/cover_reg_top/21.i2c_intr_test.2630862601
/workspace/coverage/cover_reg_top/22.i2c_intr_test.1186815539
/workspace/coverage/cover_reg_top/24.i2c_intr_test.1285215848
/workspace/coverage/cover_reg_top/25.i2c_intr_test.3417651624
/workspace/coverage/cover_reg_top/26.i2c_intr_test.3981943713
/workspace/coverage/cover_reg_top/28.i2c_intr_test.3908759923
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2159145269
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.563647204
/workspace/coverage/cover_reg_top/3.i2c_intr_test.1371007245
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1992207908
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.3436059509
/workspace/coverage/cover_reg_top/30.i2c_intr_test.663297262
/workspace/coverage/cover_reg_top/31.i2c_intr_test.2745936753
/workspace/coverage/cover_reg_top/32.i2c_intr_test.777866000
/workspace/coverage/cover_reg_top/33.i2c_intr_test.3846973592
/workspace/coverage/cover_reg_top/34.i2c_intr_test.4196998791
/workspace/coverage/cover_reg_top/35.i2c_intr_test.2733925306
/workspace/coverage/cover_reg_top/37.i2c_intr_test.602281750
/workspace/coverage/cover_reg_top/38.i2c_intr_test.4221699874
/workspace/coverage/cover_reg_top/39.i2c_intr_test.1311535524
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.484821390
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3378166907
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1512221716
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.373038999
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2180985265
/workspace/coverage/cover_reg_top/4.i2c_intr_test.811896425
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2271138146
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.1010353492
/workspace/coverage/cover_reg_top/40.i2c_intr_test.876212804
/workspace/coverage/cover_reg_top/41.i2c_intr_test.3668403243
/workspace/coverage/cover_reg_top/42.i2c_intr_test.2398979360
/workspace/coverage/cover_reg_top/43.i2c_intr_test.2649340266
/workspace/coverage/cover_reg_top/44.i2c_intr_test.472334977
/workspace/coverage/cover_reg_top/45.i2c_intr_test.2117628495
/workspace/coverage/cover_reg_top/46.i2c_intr_test.1789179407
/workspace/coverage/cover_reg_top/47.i2c_intr_test.583319053
/workspace/coverage/cover_reg_top/48.i2c_intr_test.2655488105
/workspace/coverage/cover_reg_top/49.i2c_intr_test.2001571911
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.171950658
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.3114253321
/workspace/coverage/cover_reg_top/5.i2c_intr_test.2716788952
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.718532518
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.2347139510
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3937556994
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2596419841
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.1237595718
/workspace/coverage/cover_reg_top/6.i2c_intr_test.83576843
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4129405685
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.3956711355
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2909806168
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3906303335
/workspace/coverage/cover_reg_top/7.i2c_intr_test.2389964821
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3753685323
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.2449919958
/workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3178736971
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2886159283
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.1100830979
/workspace/coverage/cover_reg_top/8.i2c_intr_test.2419718083
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4016098992
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.3079301463
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2507700041
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1697615256
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.219334161
/workspace/coverage/cover_reg_top/9.i2c_intr_test.1391946638
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.850741480
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.510264505



Total test records in report: 161
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/29.i2c_intr_test.1626691378 May 28 01:01:24 PM PDT 24 May 28 01:01:26 PM PDT 24 45843629 ps
T2 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1167749529 May 28 01:01:23 PM PDT 24 May 28 01:01:27 PM PDT 24 86807184 ps
T3 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1064542537 May 28 01:00:51 PM PDT 24 May 28 01:00:53 PM PDT 24 67921420 ps
T8 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.17691361 May 28 01:01:02 PM PDT 24 May 28 01:01:09 PM PDT 24 646296879 ps
T9 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1124075965 May 28 01:01:18 PM PDT 24 May 28 01:01:23 PM PDT 24 28499900 ps
T12 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3235773044 May 28 01:01:02 PM PDT 24 May 28 01:01:04 PM PDT 24 106612228 ps
T7 /workspace/coverage/cover_reg_top/36.i2c_intr_test.147010016 May 28 01:01:22 PM PDT 24 May 28 01:01:25 PM PDT 24 24994339 ps
T13 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2649340266 May 28 01:01:14 PM PDT 24 May 28 01:01:17 PM PDT 24 22783895 ps
T4 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.373038999 May 28 01:01:10 PM PDT 24 May 28 01:01:12 PM PDT 24 45234872 ps
T5 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.164798991 May 28 01:00:53 PM PDT 24 May 28 01:00:54 PM PDT 24 32762850 ps
T16 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3079301463 May 28 01:01:09 PM PDT 24 May 28 01:01:11 PM PDT 24 25504787 ps
T15 /workspace/coverage/cover_reg_top/35.i2c_intr_test.2733925306 May 28 01:01:21 PM PDT 24 May 28 01:01:25 PM PDT 24 26301910 ps
T6 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2596419841 May 28 01:01:15 PM PDT 24 May 28 01:01:18 PM PDT 24 116055724 ps
T10 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3937556994 May 28 01:00:50 PM PDT 24 May 28 01:00:52 PM PDT 24 313609725 ps
T11 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3447620611 May 28 01:01:01 PM PDT 24 May 28 01:01:03 PM PDT 24 130259192 ps
T14 /workspace/coverage/cover_reg_top/12.i2c_intr_test.365221253 May 28 01:01:11 PM PDT 24 May 28 01:01:13 PM PDT 24 30786382 ps
T39 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2745936753 May 28 01:01:17 PM PDT 24 May 28 01:01:20 PM PDT 24 22204646 ps
T36 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.850741480 May 28 01:01:07 PM PDT 24 May 28 01:01:08 PM PDT 24 58606594 ps
T40 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2460529308 May 28 01:01:30 PM PDT 24 May 28 01:01:33 PM PDT 24 23610842 ps
T21 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.718532518 May 28 01:00:57 PM PDT 24 May 28 01:00:59 PM PDT 24 50613402 ps
T62 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1005875909 May 28 01:01:13 PM PDT 24 May 28 01:01:15 PM PDT 24 26973755 ps
T22 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.219334161 May 28 01:01:17 PM PDT 24 May 28 01:01:23 PM PDT 24 40032879 ps
T37 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2030483069 May 28 01:01:17 PM PDT 24 May 28 01:01:21 PM PDT 24 28751536 ps
T38 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3114253321 May 28 01:01:00 PM PDT 24 May 28 01:01:01 PM PDT 24 26092553 ps
T23 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3600137876 May 28 01:01:27 PM PDT 24 May 28 01:01:30 PM PDT 24 141408466 ps
T24 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2220425031 May 28 01:01:05 PM PDT 24 May 28 01:01:07 PM PDT 24 27471651 ps
T17 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2791391382 May 28 01:01:18 PM PDT 24 May 28 01:01:22 PM PDT 24 39957731 ps
T18 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.4268365572 May 28 01:01:11 PM PDT 24 May 28 01:01:15 PM PDT 24 269617917 ps
T61 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2146296432 May 28 01:01:23 PM PDT 24 May 28 01:01:26 PM PDT 24 14988596 ps
T65 /workspace/coverage/cover_reg_top/37.i2c_intr_test.602281750 May 28 01:01:13 PM PDT 24 May 28 01:01:16 PM PDT 24 16736374 ps
T43 /workspace/coverage/cover_reg_top/38.i2c_intr_test.4221699874 May 28 01:01:15 PM PDT 24 May 28 01:01:18 PM PDT 24 28600809 ps
T63 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1285215848 May 28 01:01:22 PM PDT 24 May 28 01:01:25 PM PDT 24 23462632 ps
T19 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2644823004 May 28 01:01:16 PM PDT 24 May 28 01:01:21 PM PDT 24 1374748455 ps
T20 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2565430011 May 28 01:01:20 PM PDT 24 May 28 01:01:26 PM PDT 24 312219233 ps
T41 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2364320166 May 28 01:01:13 PM PDT 24 May 28 01:01:17 PM PDT 24 497425545 ps
T70 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4052195832 May 28 01:01:16 PM PDT 24 May 28 01:01:21 PM PDT 24 563333656 ps
T25 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2616836915 May 28 01:01:13 PM PDT 24 May 28 01:01:17 PM PDT 24 188990976 ps
T42 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3868849994 May 28 01:01:15 PM PDT 24 May 28 01:01:19 PM PDT 24 345727161 ps
T53 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3118680448 May 28 01:01:29 PM PDT 24 May 28 01:01:32 PM PDT 24 26690731 ps
T26 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1992207908 May 28 01:01:07 PM PDT 24 May 28 01:01:09 PM PDT 24 38952148 ps
T71 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2221750937 May 28 01:01:18 PM PDT 24 May 28 01:01:23 PM PDT 24 82656783 ps
T72 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.910117120 May 28 01:01:20 PM PDT 24 May 28 01:01:24 PM PDT 24 18434331 ps
T56 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.781861468 May 28 01:01:14 PM PDT 24 May 28 01:01:17 PM PDT 24 61395494 ps
T66 /workspace/coverage/cover_reg_top/34.i2c_intr_test.4196998791 May 28 01:01:12 PM PDT 24 May 28 01:01:15 PM PDT 24 17212074 ps
T73 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2726215782 May 28 01:01:14 PM PDT 24 May 28 01:01:18 PM PDT 24 57235051 ps
T27 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1174451544 May 28 01:01:17 PM PDT 24 May 28 01:01:21 PM PDT 24 29234967 ps
T28 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2544251219 May 28 01:01:10 PM PDT 24 May 28 01:01:12 PM PDT 24 288138336 ps
T74 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2489203568 May 28 01:01:16 PM PDT 24 May 28 01:01:20 PM PDT 24 163609975 ps
T75 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3621158845 May 28 01:01:12 PM PDT 24 May 28 01:01:14 PM PDT 24 35195632 ps
T76 /workspace/coverage/cover_reg_top/28.i2c_intr_test.3908759923 May 28 01:01:16 PM PDT 24 May 28 01:01:19 PM PDT 24 19417895 ps
T68 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1186815539 May 28 01:01:20 PM PDT 24 May 28 01:01:27 PM PDT 24 31917076 ps
T77 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.200743756 May 28 01:01:14 PM PDT 24 May 28 01:01:17 PM PDT 24 36209206 ps
T78 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3048606081 May 28 01:01:17 PM PDT 24 May 28 01:01:21 PM PDT 24 30994499 ps
T79 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2159145269 May 28 01:00:59 PM PDT 24 May 28 01:01:01 PM PDT 24 317499209 ps
T69 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2716788952 May 28 01:01:19 PM PDT 24 May 28 01:01:23 PM PDT 24 15874047 ps
T46 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2874569419 May 28 01:01:17 PM PDT 24 May 28 01:01:22 PM PDT 24 94764851 ps
T80 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.510264505 May 28 01:01:03 PM PDT 24 May 28 01:01:06 PM PDT 24 136301826 ps
T81 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.171950658 May 28 01:01:16 PM PDT 24 May 28 01:01:20 PM PDT 24 78789002 ps
T60 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1512221716 May 28 01:01:04 PM PDT 24 May 28 01:01:06 PM PDT 24 19483767 ps
T82 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.4221705748 May 28 01:01:24 PM PDT 24 May 28 01:01:28 PM PDT 24 155805339 ps
T83 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3833013883 May 28 01:01:10 PM PDT 24 May 28 01:01:14 PM PDT 24 886737192 ps
T84 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4129405685 May 28 01:01:04 PM PDT 24 May 28 01:01:06 PM PDT 24 152534870 ps
T85 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1608974468 May 28 01:01:08 PM PDT 24 May 28 01:01:11 PM PDT 24 97468862 ps
T45 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1579726097 May 28 01:00:53 PM PDT 24 May 28 01:00:56 PM PDT 24 133851880 ps
T67 /workspace/coverage/cover_reg_top/2.i2c_intr_test.851400107 May 28 01:00:58 PM PDT 24 May 28 01:01:00 PM PDT 24 17347730 ps
T86 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2001571911 May 28 01:01:18 PM PDT 24 May 28 01:01:21 PM PDT 24 25669866 ps
T87 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1035355042 May 28 01:01:13 PM PDT 24 May 28 01:01:16 PM PDT 24 17733054 ps
T48 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3726132939 May 28 01:01:13 PM PDT 24 May 28 01:01:17 PM PDT 24 527395146 ps
T57 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2037026364 May 28 01:01:08 PM PDT 24 May 28 01:01:11 PM PDT 24 1738658180 ps
T88 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2909806168 May 28 01:01:13 PM PDT 24 May 28 01:01:16 PM PDT 24 129182552 ps
T64 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2315987818 May 28 01:01:07 PM PDT 24 May 28 01:01:08 PM PDT 24 27118589 ps
T89 /workspace/coverage/cover_reg_top/30.i2c_intr_test.663297262 May 28 01:01:36 PM PDT 24 May 28 01:01:39 PM PDT 24 46466604 ps
T29 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1982719725 May 28 01:01:20 PM PDT 24 May 28 01:01:24 PM PDT 24 20939005 ps
T90 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1938120889 May 28 01:01:14 PM PDT 24 May 28 01:01:18 PM PDT 24 46357517 ps
T91 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3148596909 May 28 01:00:55 PM PDT 24 May 28 01:00:57 PM PDT 24 376128125 ps
T92 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.105728558 May 28 01:01:02 PM PDT 24 May 28 01:01:04 PM PDT 24 38253456 ps
T93 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.563647204 May 28 01:00:57 PM PDT 24 May 28 01:01:01 PM PDT 24 441702026 ps
T94 /workspace/coverage/cover_reg_top/16.i2c_intr_test.283380133 May 28 01:01:15 PM PDT 24 May 28 01:01:18 PM PDT 24 31489049 ps
T95 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1010353492 May 28 01:01:07 PM PDT 24 May 28 01:01:09 PM PDT 24 246391808 ps
T96 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1816931473 May 28 01:01:09 PM PDT 24 May 28 01:01:10 PM PDT 24 110123706 ps
T97 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2389964821 May 28 01:01:02 PM PDT 24 May 28 01:01:04 PM PDT 24 138302643 ps
T30 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3664474784 May 28 01:00:56 PM PDT 24 May 28 01:00:59 PM PDT 24 173906776 ps
T98 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2886159283 May 28 01:01:13 PM PDT 24 May 28 01:01:16 PM PDT 24 43007450 ps
T99 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3729288451 May 28 01:01:12 PM PDT 24 May 28 01:01:16 PM PDT 24 75925416 ps
T100 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1054207717 May 28 01:01:25 PM PDT 24 May 28 01:01:27 PM PDT 24 28423809 ps
T101 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1100830979 May 28 01:01:15 PM PDT 24 May 28 01:01:18 PM PDT 24 16823112 ps
T47 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2394864619 May 28 01:01:09 PM PDT 24 May 28 01:01:12 PM PDT 24 762937791 ps
T49 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2507700041 May 28 01:01:07 PM PDT 24 May 28 01:01:09 PM PDT 24 160060816 ps
T102 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.679413364 May 28 01:01:22 PM PDT 24 May 28 01:01:26 PM PDT 24 30861742 ps
T103 /workspace/coverage/cover_reg_top/6.i2c_intr_test.83576843 May 28 01:00:55 PM PDT 24 May 28 01:00:56 PM PDT 24 46543938 ps
T104 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2135685270 May 28 01:01:09 PM PDT 24 May 28 01:01:11 PM PDT 24 147371495 ps
T105 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4016098992 May 28 01:00:58 PM PDT 24 May 28 01:01:00 PM PDT 24 38499168 ps
T106 /workspace/coverage/cover_reg_top/8.i2c_intr_test.2419718083 May 28 01:00:56 PM PDT 24 May 28 01:00:58 PM PDT 24 27938580 ps
T107 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3436059509 May 28 01:00:57 PM PDT 24 May 28 01:01:00 PM PDT 24 254355517 ps
T108 /workspace/coverage/cover_reg_top/27.i2c_intr_test.183307586 May 28 01:01:34 PM PDT 24 May 28 01:01:36 PM PDT 24 35205336 ps
T109 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3714526965 May 28 01:01:18 PM PDT 24 May 28 01:01:23 PM PDT 24 82239190 ps
T110 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.138510680 May 28 01:01:18 PM PDT 24 May 28 01:01:22 PM PDT 24 27260180 ps
T54 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.29849232 May 28 01:01:18 PM PDT 24 May 28 01:01:21 PM PDT 24 27887258 ps
T111 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3956711355 May 28 01:01:19 PM PDT 24 May 28 01:01:25 PM PDT 24 56481146 ps
T112 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1237595718 May 28 01:01:06 PM PDT 24 May 28 01:01:08 PM PDT 24 53401170 ps
T113 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2630862601 May 28 01:01:25 PM PDT 24 May 28 01:01:27 PM PDT 24 42502585 ps
T114 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3111723105 May 28 01:01:10 PM PDT 24 May 28 01:01:12 PM PDT 24 208211759 ps
T115 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1175250252 May 28 01:00:56 PM PDT 24 May 28 01:00:59 PM PDT 24 1184538329 ps
T116 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3425981245 May 28 01:01:11 PM PDT 24 May 28 01:01:13 PM PDT 24 18308129 ps
T58 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1131977463 May 28 01:01:08 PM PDT 24 May 28 01:01:10 PM PDT 24 33328012 ps
T117 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2698909295 May 28 01:01:09 PM PDT 24 May 28 01:01:11 PM PDT 24 107327110 ps
T118 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3229267096 May 28 01:01:02 PM PDT 24 May 28 01:01:04 PM PDT 24 36070962 ps
T31 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2180985265 May 28 01:01:04 PM PDT 24 May 28 01:01:06 PM PDT 24 26424358 ps
T50 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4044761670 May 28 01:01:35 PM PDT 24 May 28 01:01:38 PM PDT 24 113458472 ps
T119 /workspace/coverage/cover_reg_top/33.i2c_intr_test.3846973592 May 28 01:01:23 PM PDT 24 May 28 01:01:26 PM PDT 24 18503145 ps
T120 /workspace/coverage/cover_reg_top/17.i2c_intr_test.426659229 May 28 01:01:19 PM PDT 24 May 28 01:01:23 PM PDT 24 15963034 ps
T121 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2749003902 May 28 01:01:08 PM PDT 24 May 28 01:01:10 PM PDT 24 40922059 ps
T122 /workspace/coverage/cover_reg_top/47.i2c_intr_test.583319053 May 28 01:01:15 PM PDT 24 May 28 01:01:18 PM PDT 24 43187457 ps
T123 /workspace/coverage/cover_reg_top/1.i2c_intr_test.397575802 May 28 01:01:08 PM PDT 24 May 28 01:01:10 PM PDT 24 18973933 ps
T124 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1962878504 May 28 01:01:20 PM PDT 24 May 28 01:01:24 PM PDT 24 102393097 ps
T125 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1406831453 May 28 01:01:13 PM PDT 24 May 28 01:01:16 PM PDT 24 77310287 ps
T126 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2733237665 May 28 01:01:11 PM PDT 24 May 28 01:01:13 PM PDT 24 18668663 ps
T127 /workspace/coverage/cover_reg_top/40.i2c_intr_test.876212804 May 28 01:01:18 PM PDT 24 May 28 01:01:21 PM PDT 24 54990896 ps
T59 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2484928297 May 28 01:00:55 PM PDT 24 May 28 01:00:57 PM PDT 24 20730975 ps
T128 /workspace/coverage/cover_reg_top/26.i2c_intr_test.3981943713 May 28 01:01:27 PM PDT 24 May 28 01:01:30 PM PDT 24 51711224 ps
T129 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2271138146 May 28 01:01:19 PM PDT 24 May 28 01:01:27 PM PDT 24 40346843 ps
T130 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3753685323 May 28 01:01:21 PM PDT 24 May 28 01:01:25 PM PDT 24 23852961 ps
T32 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1409916172 May 28 01:01:18 PM PDT 24 May 28 01:01:22 PM PDT 24 30789145 ps
T131 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2117628495 May 28 01:01:30 PM PDT 24 May 28 01:01:33 PM PDT 24 23646954 ps
T132 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1817824609 May 28 01:01:22 PM PDT 24 May 28 01:01:25 PM PDT 24 51837084 ps
T133 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2655488105 May 28 01:01:13 PM PDT 24 May 28 01:01:16 PM PDT 24 22028799 ps
T134 /workspace/coverage/cover_reg_top/44.i2c_intr_test.472334977 May 28 01:01:12 PM PDT 24 May 28 01:01:14 PM PDT 24 23392329 ps
T33 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2948435338 May 28 01:01:04 PM PDT 24 May 28 01:01:06 PM PDT 24 49741300 ps
T34 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2810031475 May 28 01:01:28 PM PDT 24 May 28 01:01:30 PM PDT 24 21580944 ps
T135 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3527237617 May 28 01:01:11 PM PDT 24 May 28 01:01:16 PM PDT 24 3026084902 ps
T136 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1789179407 May 28 01:01:11 PM PDT 24 May 28 01:01:13 PM PDT 24 29873407 ps
T137 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3668403243 May 28 01:01:34 PM PDT 24 May 28 01:01:36 PM PDT 24 15364552 ps
T138 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.641578118 May 28 01:01:11 PM PDT 24 May 28 01:01:14 PM PDT 24 41150641 ps
T139 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1391946638 May 28 01:01:13 PM PDT 24 May 28 01:01:16 PM PDT 24 115535173 ps
T140 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2773565003 May 28 01:01:16 PM PDT 24 May 28 01:01:20 PM PDT 24 165604172 ps
T141 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3906303335 May 28 01:01:13 PM PDT 24 May 28 01:01:16 PM PDT 24 33913136 ps
T35 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.484821390 May 28 01:00:51 PM PDT 24 May 28 01:00:54 PM PDT 24 265789558 ps
T142 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2347139510 May 28 01:01:15 PM PDT 24 May 28 01:01:20 PM PDT 24 500223894 ps
T51 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3768588058 May 28 01:01:02 PM PDT 24 May 28 01:01:05 PM PDT 24 603352249 ps
T143 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1436619842 May 28 01:00:53 PM PDT 24 May 28 01:00:54 PM PDT 24 55355033 ps
T144 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2449919958 May 28 01:01:11 PM PDT 24 May 28 01:01:14 PM PDT 24 110226212 ps
T145 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3417651624 May 28 01:01:28 PM PDT 24 May 28 01:01:31 PM PDT 24 169729391 ps
T146 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2398979360 May 28 01:01:09 PM PDT 24 May 28 01:01:11 PM PDT 24 39279986 ps
T147 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3378166907 May 28 01:01:18 PM PDT 24 May 28 01:01:25 PM PDT 24 448572655 ps
T148 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2543067144 May 28 01:01:15 PM PDT 24 May 28 01:01:19 PM PDT 24 322770928 ps
T149 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1371007245 May 28 01:01:17 PM PDT 24 May 28 01:01:20 PM PDT 24 18955310 ps
T150 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1334190555 May 28 01:01:06 PM PDT 24 May 28 01:01:08 PM PDT 24 23527389 ps
T151 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3178736971 May 28 01:01:06 PM PDT 24 May 28 01:01:09 PM PDT 24 277667462 ps
T44 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2639401551 May 28 01:00:50 PM PDT 24 May 28 01:00:52 PM PDT 24 34753766 ps
T152 /workspace/coverage/cover_reg_top/4.i2c_intr_test.811896425 May 28 01:01:18 PM PDT 24 May 28 01:01:22 PM PDT 24 16948495 ps
T153 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1681313927 May 28 01:01:18 PM PDT 24 May 28 01:01:24 PM PDT 24 138112292 ps
T55 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2390225735 May 28 01:01:20 PM PDT 24 May 28 01:01:24 PM PDT 24 55374407 ps
T154 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.673881592 May 28 01:01:20 PM PDT 24 May 28 01:01:24 PM PDT 24 55209884 ps
T155 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1697615256 May 28 01:01:06 PM PDT 24 May 28 01:01:08 PM PDT 24 29804810 ps
T156 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.421329821 May 28 01:00:57 PM PDT 24 May 28 01:00:58 PM PDT 24 25572484 ps
T157 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1329933975 May 28 01:00:51 PM PDT 24 May 28 01:00:53 PM PDT 24 131872412 ps
T158 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.198043041 May 28 01:01:20 PM PDT 24 May 28 01:01:24 PM PDT 24 238770253 ps
T159 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1311535524 May 28 01:01:25 PM PDT 24 May 28 01:01:28 PM PDT 24 18822055 ps
T52 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3994455014 May 28 01:00:59 PM PDT 24 May 28 01:01:03 PM PDT 24 292238629 ps
T160 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3012689021 May 28 01:01:30 PM PDT 24 May 28 01:01:33 PM PDT 24 32095679 ps
T161 /workspace/coverage/cover_reg_top/32.i2c_intr_test.777866000 May 28 01:01:13 PM PDT 24 May 28 01:01:15 PM PDT 24 15861170 ps

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.164798991
Short name T5
Test name
Test status
Simulation time 32762850 ps
CPU time 0.91 seconds
Started May 28 01:00:53 PM PDT 24
Finished May 28 01:00:54 PM PDT 24
Peak memory 204216 kb
Host smart-e68e03c9-c525-4307-8e02-37de9cce6dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164798991 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.164798991
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.147010016
Short name T7
Test name
Test status
Simulation time 24994339 ps
CPU time 0.74 seconds
Started May 28 01:01:22 PM PDT 24
Finished May 28 01:01:25 PM PDT 24
Peak memory 204244 kb
Host smart-051374e5-c0f9-4935-a765-06da947f8142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147010016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.147010016
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3447620611
Short name T11
Test name
Test status
Simulation time 130259192 ps
CPU time 1.58 seconds
Started May 28 01:01:01 PM PDT 24
Finished May 28 01:01:03 PM PDT 24
Peak memory 204520 kb
Host smart-c4563977-63ca-49c6-bdd3-cf03f60061a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447620611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3447620611
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1626691378
Short name T1
Test name
Test status
Simulation time 45843629 ps
CPU time 0.68 seconds
Started May 28 01:01:24 PM PDT 24
Finished May 28 01:01:26 PM PDT 24
Peak memory 204164 kb
Host smart-be243096-aace-494a-a5f0-fa3e913dcbfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626691378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1626691378
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1124075965
Short name T9
Test name
Test status
Simulation time 28499900 ps
CPU time 0.77 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:23 PM PDT 24
Peak memory 204296 kb
Host smart-e3b08e6f-8ebf-4d9e-9a3a-542e9e528b27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124075965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1124075965
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2644823004
Short name T19
Test name
Test status
Simulation time 1374748455 ps
CPU time 2.48 seconds
Started May 28 01:01:16 PM PDT 24
Finished May 28 01:01:21 PM PDT 24
Peak memory 204504 kb
Host smart-97700d5f-e1f8-4a1e-9491-342f6287a853
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644823004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2644823004
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2146296432
Short name T61
Test name
Test status
Simulation time 14988596 ps
CPU time 0.65 seconds
Started May 28 01:01:23 PM PDT 24
Finished May 28 01:01:26 PM PDT 24
Peak memory 204220 kb
Host smart-b287bcdd-9d93-4927-ba0b-c699e3f92ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146296432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2146296432
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2616836915
Short name T25
Test name
Test status
Simulation time 188990976 ps
CPU time 1.11 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:17 PM PDT 24
Peak memory 204504 kb
Host smart-8d5c9364-ea57-4ce7-aee5-a1345ad97ac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616836915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2616836915
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.426659229
Short name T120
Test name
Test status
Simulation time 15963034 ps
CPU time 0.71 seconds
Started May 28 01:01:19 PM PDT 24
Finished May 28 01:01:23 PM PDT 24
Peak memory 204256 kb
Host smart-7ebaa3df-2bce-4990-a551-86fa988805bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426659229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.426659229
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2565430011
Short name T20
Test name
Test status
Simulation time 312219233 ps
CPU time 2.3 seconds
Started May 28 01:01:20 PM PDT 24
Finished May 28 01:01:26 PM PDT 24
Peak memory 204452 kb
Host smart-c759bcaa-6e20-463d-b3a7-84956f5a3465
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565430011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2565430011
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2544251219
Short name T28
Test name
Test status
Simulation time 288138336 ps
CPU time 0.95 seconds
Started May 28 01:01:10 PM PDT 24
Finished May 28 01:01:12 PM PDT 24
Peak memory 204296 kb
Host smart-55fbf4f1-10cc-4cfb-bfab-d9c1c7817f27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544251219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2544251219
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.183307586
Short name T108
Test name
Test status
Simulation time 35205336 ps
CPU time 0.72 seconds
Started May 28 01:01:34 PM PDT 24
Finished May 28 01:01:36 PM PDT 24
Peak memory 204188 kb
Host smart-f7b84072-66dc-4923-8482-72a4a733107f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183307586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.183307586
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2639401551
Short name T44
Test name
Test status
Simulation time 34753766 ps
CPU time 0.69 seconds
Started May 28 01:00:50 PM PDT 24
Finished May 28 01:00:52 PM PDT 24
Peak memory 204064 kb
Host smart-691518de-c01f-4963-b561-58530398a0f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639401551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2639401551
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3425981245
Short name T116
Test name
Test status
Simulation time 18308129 ps
CPU time 0.67 seconds
Started May 28 01:01:11 PM PDT 24
Finished May 28 01:01:13 PM PDT 24
Peak memory 204252 kb
Host smart-27cfc337-9489-4bd6-9cd0-0f0be8ef42b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425981245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3425981245
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.781861468
Short name T56
Test name
Test status
Simulation time 61395494 ps
CPU time 0.85 seconds
Started May 28 01:01:14 PM PDT 24
Finished May 28 01:01:17 PM PDT 24
Peak memory 204308 kb
Host smart-4e84d225-a431-4433-9b6d-2be121db2bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781861468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.781861468
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.29849232
Short name T54
Test name
Test status
Simulation time 27887258 ps
CPU time 0.72 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:21 PM PDT 24
Peak memory 204696 kb
Host smart-4e2dfca2-98f0-46d8-bef3-8fd4a3bf2f0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29849232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.29849232
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2484928297
Short name T59
Test name
Test status
Simulation time 20730975 ps
CPU time 0.79 seconds
Started May 28 01:00:55 PM PDT 24
Finished May 28 01:00:57 PM PDT 24
Peak memory 204284 kb
Host smart-6cc53af1-407a-4c81-b2df-718bdaeffc88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484928297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2484928297
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2874569419
Short name T46
Test name
Test status
Simulation time 94764851 ps
CPU time 2.26 seconds
Started May 28 01:01:17 PM PDT 24
Finished May 28 01:01:22 PM PDT 24
Peak memory 204564 kb
Host smart-6d5a947d-33aa-4ea9-be59-bfeede5d0681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874569419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2874569419
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3768588058
Short name T51
Test name
Test status
Simulation time 603352249 ps
CPU time 2.44 seconds
Started May 28 01:01:02 PM PDT 24
Finished May 28 01:01:05 PM PDT 24
Peak memory 204508 kb
Host smart-8a0035f0-184e-420d-af3c-4f77a4f74a74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768588058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3768588058
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2394864619
Short name T47
Test name
Test status
Simulation time 762937791 ps
CPU time 1.54 seconds
Started May 28 01:01:09 PM PDT 24
Finished May 28 01:01:12 PM PDT 24
Peak memory 204492 kb
Host smart-63c87ace-6d59-4aa4-aea3-5024c253b9aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394864619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2394864619
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1579726097
Short name T45
Test name
Test status
Simulation time 133851880 ps
CPU time 2.47 seconds
Started May 28 01:00:53 PM PDT 24
Finished May 28 01:00:56 PM PDT 24
Peak memory 204564 kb
Host smart-fcd910e2-205f-4ea8-9967-552b21f567a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579726097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1579726097
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3664474784
Short name T30
Test name
Test status
Simulation time 173906776 ps
CPU time 2.05 seconds
Started May 28 01:00:56 PM PDT 24
Finished May 28 01:00:59 PM PDT 24
Peak memory 204412 kb
Host smart-d601acbb-3527-4fde-b851-735372211838
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664474784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3664474784
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.17691361
Short name T8
Test name
Test status
Simulation time 646296879 ps
CPU time 6.28 seconds
Started May 28 01:01:02 PM PDT 24
Finished May 28 01:01:09 PM PDT 24
Peak memory 204456 kb
Host smart-aa335936-bcbc-4082-9296-e10cd89f0af7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17691361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.17691361
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1436619842
Short name T143
Test name
Test status
Simulation time 55355033 ps
CPU time 0.69 seconds
Started May 28 01:00:53 PM PDT 24
Finished May 28 01:00:54 PM PDT 24
Peak memory 204208 kb
Host smart-08eaaeb2-bfb9-4cbd-ace7-064f64c53dad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436619842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1436619842
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3148596909
Short name T91
Test name
Test status
Simulation time 376128125 ps
CPU time 0.81 seconds
Started May 28 01:00:55 PM PDT 24
Finished May 28 01:00:57 PM PDT 24
Peak memory 204292 kb
Host smart-e5eb47f1-8228-4a8f-ba36-13f7ac10b0ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148596909 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3148596909
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1409916172
Short name T32
Test name
Test status
Simulation time 30789145 ps
CPU time 0.83 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:22 PM PDT 24
Peak memory 204284 kb
Host smart-9818057c-c8c7-4612-8a0a-6a662fd4b9a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409916172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1409916172
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3235773044
Short name T12
Test name
Test status
Simulation time 106612228 ps
CPU time 0.74 seconds
Started May 28 01:01:02 PM PDT 24
Finished May 28 01:01:04 PM PDT 24
Peak memory 204320 kb
Host smart-a4146583-5d5c-44b3-ac1b-5c9c9a069dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235773044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3235773044
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1064542537
Short name T3
Test name
Test status
Simulation time 67921420 ps
CPU time 1.46 seconds
Started May 28 01:00:51 PM PDT 24
Finished May 28 01:00:53 PM PDT 24
Peak memory 204476 kb
Host smart-24c3ad4f-746d-4708-813d-9e943c60cb5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064542537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1064542537
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3994455014
Short name T52
Test name
Test status
Simulation time 292238629 ps
CPU time 2.41 seconds
Started May 28 01:00:59 PM PDT 24
Finished May 28 01:01:03 PM PDT 24
Peak memory 204468 kb
Host smart-3426b89d-bd42-4b7e-b603-1d2cce9aa8e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994455014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3994455014
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2948435338
Short name T33
Test name
Test status
Simulation time 49741300 ps
CPU time 1.39 seconds
Started May 28 01:01:04 PM PDT 24
Finished May 28 01:01:06 PM PDT 24
Peak memory 204468 kb
Host smart-3fc99ab7-82f4-48ca-ae18-f65a56d32ba3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948435338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2948435338
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3527237617
Short name T135
Test name
Test status
Simulation time 3026084902 ps
CPU time 3.35 seconds
Started May 28 01:01:11 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204440 kb
Host smart-c0588229-20ef-47a9-917a-c0c0bd12e55a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527237617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3527237617
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.200743756
Short name T77
Test name
Test status
Simulation time 36209206 ps
CPU time 0.69 seconds
Started May 28 01:01:14 PM PDT 24
Finished May 28 01:01:17 PM PDT 24
Peak memory 204320 kb
Host smart-41d0b209-0ecc-4ed6-bf9d-fe3212097bc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200743756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.200743756
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1329933975
Short name T157
Test name
Test status
Simulation time 131872412 ps
CPU time 0.95 seconds
Started May 28 01:00:51 PM PDT 24
Finished May 28 01:00:53 PM PDT 24
Peak memory 204336 kb
Host smart-a5743e41-d853-41ed-8470-dd96d89320d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329933975 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1329933975
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1334190555
Short name T150
Test name
Test status
Simulation time 23527389 ps
CPU time 0.69 seconds
Started May 28 01:01:06 PM PDT 24
Finished May 28 01:01:08 PM PDT 24
Peak memory 204208 kb
Host smart-03600f40-3c9b-4899-997f-1c0aba994065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334190555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1334190555
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.397575802
Short name T123
Test name
Test status
Simulation time 18973933 ps
CPU time 0.68 seconds
Started May 28 01:01:08 PM PDT 24
Finished May 28 01:01:10 PM PDT 24
Peak memory 204248 kb
Host smart-ab5f0fef-f3df-4884-878d-d4ad8639ebfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397575802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.397575802
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1962878504
Short name T124
Test name
Test status
Simulation time 102393097 ps
CPU time 0.91 seconds
Started May 28 01:01:20 PM PDT 24
Finished May 28 01:01:24 PM PDT 24
Peak memory 204280 kb
Host smart-77adf86e-04e3-4af3-9944-446d51cceb7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962878504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1962878504
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2543067144
Short name T148
Test name
Test status
Simulation time 322770928 ps
CPU time 1.96 seconds
Started May 28 01:01:15 PM PDT 24
Finished May 28 01:01:19 PM PDT 24
Peak memory 204484 kb
Host smart-b49ddb54-6305-483c-968f-271cff70ef0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543067144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2543067144
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3229267096
Short name T118
Test name
Test status
Simulation time 36070962 ps
CPU time 1.14 seconds
Started May 28 01:01:02 PM PDT 24
Finished May 28 01:01:04 PM PDT 24
Peak memory 204372 kb
Host smart-ae0ecf60-ff9c-4d14-8275-84d46e217ac2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229267096 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3229267096
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1174451544
Short name T27
Test name
Test status
Simulation time 29234967 ps
CPU time 0.76 seconds
Started May 28 01:01:17 PM PDT 24
Finished May 28 01:01:21 PM PDT 24
Peak memory 204176 kb
Host smart-8a1ad140-8b5e-4553-8e6c-90d504a27909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174451544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1174451544
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1131977463
Short name T58
Test name
Test status
Simulation time 33328012 ps
CPU time 0.89 seconds
Started May 28 01:01:08 PM PDT 24
Finished May 28 01:01:10 PM PDT 24
Peak memory 204244 kb
Host smart-a8994015-1b39-47cd-af0b-2d09a46ba8a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131977463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1131977463
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2364320166
Short name T41
Test name
Test status
Simulation time 497425545 ps
CPU time 1.36 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:17 PM PDT 24
Peak memory 204544 kb
Host smart-9ae93632-8cb0-4e1e-8802-e65d96964f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364320166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2364320166
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3868849994
Short name T42
Test name
Test status
Simulation time 345727161 ps
CPU time 1.57 seconds
Started May 28 01:01:15 PM PDT 24
Finished May 28 01:01:19 PM PDT 24
Peak memory 204536 kb
Host smart-f036be04-b787-4b03-808b-b1c91366838f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868849994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3868849994
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.910117120
Short name T72
Test name
Test status
Simulation time 18434331 ps
CPU time 0.76 seconds
Started May 28 01:01:20 PM PDT 24
Finished May 28 01:01:24 PM PDT 24
Peak memory 204304 kb
Host smart-5b9344e2-3cb3-4615-b838-3e982390b06e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910117120 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.910117120
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2220425031
Short name T24
Test name
Test status
Simulation time 27471651 ps
CPU time 0.82 seconds
Started May 28 01:01:05 PM PDT 24
Finished May 28 01:01:07 PM PDT 24
Peak memory 204116 kb
Host smart-04f30fd8-fc58-4c90-9012-221a80d542fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220425031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2220425031
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1938120889
Short name T90
Test name
Test status
Simulation time 46357517 ps
CPU time 0.66 seconds
Started May 28 01:01:14 PM PDT 24
Finished May 28 01:01:18 PM PDT 24
Peak memory 204252 kb
Host smart-9ab46365-3466-40e0-933f-b0124867ddbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938120889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1938120889
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1167749529
Short name T2
Test name
Test status
Simulation time 86807184 ps
CPU time 1.86 seconds
Started May 28 01:01:23 PM PDT 24
Finished May 28 01:01:27 PM PDT 24
Peak memory 204548 kb
Host smart-b8275773-9e5e-495f-ac08-2d5c593f368e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167749529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1167749529
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.105728558
Short name T92
Test name
Test status
Simulation time 38253456 ps
CPU time 0.97 seconds
Started May 28 01:01:02 PM PDT 24
Finished May 28 01:01:04 PM PDT 24
Peak memory 204288 kb
Host smart-2b1d68b4-293c-4a08-930f-c10e70ca5e9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105728558 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.105728558
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1406831453
Short name T125
Test name
Test status
Simulation time 77310287 ps
CPU time 0.78 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204308 kb
Host smart-11f61624-c746-4082-abf7-1ec570492a1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406831453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1406831453
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.365221253
Short name T14
Test name
Test status
Simulation time 30786382 ps
CPU time 0.66 seconds
Started May 28 01:01:11 PM PDT 24
Finished May 28 01:01:13 PM PDT 24
Peak memory 204248 kb
Host smart-f23ebad7-eb69-4fff-a517-27104ea55295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365221253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.365221253
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.4052195832
Short name T70
Test name
Test status
Simulation time 563333656 ps
CPU time 2.16 seconds
Started May 28 01:01:16 PM PDT 24
Finished May 28 01:01:21 PM PDT 24
Peak memory 204532 kb
Host smart-4b289103-e54d-4fb7-b58d-87a68f4e09ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052195832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.4052195832
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2773565003
Short name T140
Test name
Test status
Simulation time 165604172 ps
CPU time 1.45 seconds
Started May 28 01:01:16 PM PDT 24
Finished May 28 01:01:20 PM PDT 24
Peak memory 204552 kb
Host smart-86e3f1a8-b683-4357-8deb-85f289024def
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773565003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2773565003
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3118680448
Short name T53
Test name
Test status
Simulation time 26690731 ps
CPU time 0.77 seconds
Started May 28 01:01:29 PM PDT 24
Finished May 28 01:01:32 PM PDT 24
Peak memory 204464 kb
Host smart-c397e306-ce88-4a98-89ce-e7225012befc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118680448 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3118680448
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2315987818
Short name T64
Test name
Test status
Simulation time 27118589 ps
CPU time 0.65 seconds
Started May 28 01:01:07 PM PDT 24
Finished May 28 01:01:08 PM PDT 24
Peak memory 204172 kb
Host smart-28aef4a7-150c-4dea-b38d-d155183f3b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315987818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2315987818
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1608974468
Short name T85
Test name
Test status
Simulation time 97468862 ps
CPU time 1.22 seconds
Started May 28 01:01:08 PM PDT 24
Finished May 28 01:01:11 PM PDT 24
Peak memory 204412 kb
Host smart-474fac0a-c880-454c-a8e8-97cbdafa3637
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608974468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1608974468
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3833013883
Short name T83
Test name
Test status
Simulation time 886737192 ps
CPU time 2.63 seconds
Started May 28 01:01:10 PM PDT 24
Finished May 28 01:01:14 PM PDT 24
Peak memory 204616 kb
Host smart-3ff99537-53ba-49f9-9db7-e141c5bfc8db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833013883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3833013883
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2135685270
Short name T104
Test name
Test status
Simulation time 147371495 ps
CPU time 1.33 seconds
Started May 28 01:01:09 PM PDT 24
Finished May 28 01:01:11 PM PDT 24
Peak memory 204508 kb
Host smart-7079a705-525e-48ca-a7af-b9e29ad1ccd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135685270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2135685270
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.198043041
Short name T158
Test name
Test status
Simulation time 238770253 ps
CPU time 0.99 seconds
Started May 28 01:01:20 PM PDT 24
Finished May 28 01:01:24 PM PDT 24
Peak memory 204352 kb
Host smart-461fb4ed-6ea7-41a1-9c21-b92f3ee1cb46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198043041 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.198043041
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2810031475
Short name T34
Test name
Test status
Simulation time 21580944 ps
CPU time 0.75 seconds
Started May 28 01:01:28 PM PDT 24
Finished May 28 01:01:30 PM PDT 24
Peak memory 204636 kb
Host smart-acb5ba5a-c9de-457c-9007-56b98be6233d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810031475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2810031475
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1816931473
Short name T96
Test name
Test status
Simulation time 110123706 ps
CPU time 0.67 seconds
Started May 28 01:01:09 PM PDT 24
Finished May 28 01:01:10 PM PDT 24
Peak memory 204264 kb
Host smart-9b3fe027-2d1e-4676-a892-0148a4c4521e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816931473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1816931473
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3048606081
Short name T78
Test name
Test status
Simulation time 30994499 ps
CPU time 0.85 seconds
Started May 28 01:01:17 PM PDT 24
Finished May 28 01:01:21 PM PDT 24
Peak memory 204280 kb
Host smart-ac8deca2-a2b7-4203-bbc2-815722d33cee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048606081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.3048606081
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.138510680
Short name T110
Test name
Test status
Simulation time 27260180 ps
CPU time 1.45 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:22 PM PDT 24
Peak memory 204580 kb
Host smart-70ea0959-9049-4e91-9a6a-cf962cb4a5fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138510680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.138510680
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3726132939
Short name T48
Test name
Test status
Simulation time 527395146 ps
CPU time 2.23 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:17 PM PDT 24
Peak memory 204536 kb
Host smart-0fe0c48d-4f41-4455-8518-8a2ce935ba7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726132939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3726132939
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3012689021
Short name T160
Test name
Test status
Simulation time 32095679 ps
CPU time 0.83 seconds
Started May 28 01:01:30 PM PDT 24
Finished May 28 01:01:33 PM PDT 24
Peak memory 204388 kb
Host smart-8a1ba006-00d4-4b96-889a-b9a96bcc99a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012689021 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3012689021
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1035355042
Short name T87
Test name
Test status
Simulation time 17733054 ps
CPU time 0.7 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204224 kb
Host smart-37f0d75f-b24b-4adb-a219-519356583524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035355042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1035355042
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1005875909
Short name T62
Test name
Test status
Simulation time 26973755 ps
CPU time 0.67 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:15 PM PDT 24
Peak memory 204252 kb
Host smart-f15ca95c-2525-45f5-a30c-9633e0baf1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005875909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1005875909
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.641578118
Short name T138
Test name
Test status
Simulation time 41150641 ps
CPU time 0.92 seconds
Started May 28 01:01:11 PM PDT 24
Finished May 28 01:01:14 PM PDT 24
Peak memory 204276 kb
Host smart-cb61c1c4-ea3d-40c1-b59b-a537409b8a11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641578118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.641578118
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.4044761670
Short name T50
Test name
Test status
Simulation time 113458472 ps
CPU time 1.46 seconds
Started May 28 01:01:35 PM PDT 24
Finished May 28 01:01:38 PM PDT 24
Peak memory 204560 kb
Host smart-95394e52-6db9-4e2b-b440-8958fb2b15f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044761670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.4044761670
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2221750937
Short name T71
Test name
Test status
Simulation time 82656783 ps
CPU time 1.16 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:23 PM PDT 24
Peak memory 204600 kb
Host smart-2c8c4fa2-95b9-4e6e-a82b-7e331cbe567c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221750937 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2221750937
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1982719725
Short name T29
Test name
Test status
Simulation time 20939005 ps
CPU time 0.7 seconds
Started May 28 01:01:20 PM PDT 24
Finished May 28 01:01:24 PM PDT 24
Peak memory 204276 kb
Host smart-89f2893b-3b7f-4c07-aedf-b566719a96d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982719725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1982719725
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.283380133
Short name T94
Test name
Test status
Simulation time 31489049 ps
CPU time 0.64 seconds
Started May 28 01:01:15 PM PDT 24
Finished May 28 01:01:18 PM PDT 24
Peak memory 204248 kb
Host smart-b9bffc0b-1a1e-4cce-bfb8-68e007838110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283380133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.283380133
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2390225735
Short name T55
Test name
Test status
Simulation time 55374407 ps
CPU time 0.86 seconds
Started May 28 01:01:20 PM PDT 24
Finished May 28 01:01:24 PM PDT 24
Peak memory 204292 kb
Host smart-68c4380a-61df-4dec-a38e-867f3bb6a5f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390225735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.2390225735
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.4268365572
Short name T18
Test name
Test status
Simulation time 269617917 ps
CPU time 2.55 seconds
Started May 28 01:01:11 PM PDT 24
Finished May 28 01:01:15 PM PDT 24
Peak memory 204468 kb
Host smart-6e85e28b-ad47-41af-abb8-75a1221492d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268365572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.4268365572
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3111723105
Short name T114
Test name
Test status
Simulation time 208211759 ps
CPU time 1.53 seconds
Started May 28 01:01:10 PM PDT 24
Finished May 28 01:01:12 PM PDT 24
Peak memory 204468 kb
Host smart-0b658f55-3bfa-4d1a-b8aa-2de04b34e409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111723105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3111723105
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2489203568
Short name T74
Test name
Test status
Simulation time 163609975 ps
CPU time 0.93 seconds
Started May 28 01:01:16 PM PDT 24
Finished May 28 01:01:20 PM PDT 24
Peak memory 204400 kb
Host smart-c9eac5d0-7096-4f44-8a28-ea8b7947cfa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489203568 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2489203568
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3600137876
Short name T23
Test name
Test status
Simulation time 141408466 ps
CPU time 0.82 seconds
Started May 28 01:01:27 PM PDT 24
Finished May 28 01:01:30 PM PDT 24
Peak memory 204212 kb
Host smart-39d9004a-1476-420b-a5e5-e26d4ca4fae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600137876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3600137876
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2698909295
Short name T117
Test name
Test status
Simulation time 107327110 ps
CPU time 0.89 seconds
Started May 28 01:01:09 PM PDT 24
Finished May 28 01:01:11 PM PDT 24
Peak memory 204268 kb
Host smart-07e2be3e-b295-496d-9835-e9ab9f9f6dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698909295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2698909295
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.679413364
Short name T102
Test name
Test status
Simulation time 30861742 ps
CPU time 1.48 seconds
Started May 28 01:01:22 PM PDT 24
Finished May 28 01:01:26 PM PDT 24
Peak memory 204512 kb
Host smart-331cbcf5-0f8e-4592-b70a-63589aa5ff28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679413364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.679413364
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2791391382
Short name T17
Test name
Test status
Simulation time 39957731 ps
CPU time 1.17 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:22 PM PDT 24
Peak memory 204788 kb
Host smart-680a7256-d6c5-49b7-8f28-dc2740458282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791391382 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2791391382
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.673881592
Short name T154
Test name
Test status
Simulation time 55209884 ps
CPU time 0.77 seconds
Started May 28 01:01:20 PM PDT 24
Finished May 28 01:01:24 PM PDT 24
Peak memory 204312 kb
Host smart-4b632314-a638-4d69-959b-817cdb9c6952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673881592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.673881592
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2733237665
Short name T126
Test name
Test status
Simulation time 18668663 ps
CPU time 0.68 seconds
Started May 28 01:01:11 PM PDT 24
Finished May 28 01:01:13 PM PDT 24
Peak memory 204636 kb
Host smart-3715cfc3-6f03-4af4-9c2c-3e8dfe90ed92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733237665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2733237665
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2030483069
Short name T37
Test name
Test status
Simulation time 28751536 ps
CPU time 1.11 seconds
Started May 28 01:01:17 PM PDT 24
Finished May 28 01:01:21 PM PDT 24
Peak memory 204536 kb
Host smart-9467b8d2-bb59-4d26-9bbb-fd3c897af384
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030483069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2030483069
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3714526965
Short name T109
Test name
Test status
Simulation time 82239190 ps
CPU time 2.15 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:23 PM PDT 24
Peak memory 204928 kb
Host smart-69acd743-fa52-43ac-a230-7836067ae416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714526965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3714526965
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3729288451
Short name T99
Test name
Test status
Simulation time 75925416 ps
CPU time 1.16 seconds
Started May 28 01:01:12 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 203520 kb
Host smart-23343ac8-6a4a-40e3-94fe-692a2a48d84d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729288451 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3729288451
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1817824609
Short name T132
Test name
Test status
Simulation time 51837084 ps
CPU time 0.72 seconds
Started May 28 01:01:22 PM PDT 24
Finished May 28 01:01:25 PM PDT 24
Peak memory 204212 kb
Host smart-cbd3b03c-069e-488c-9987-95bdddcfdeeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817824609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1817824609
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1054207717
Short name T100
Test name
Test status
Simulation time 28423809 ps
CPU time 0.67 seconds
Started May 28 01:01:25 PM PDT 24
Finished May 28 01:01:27 PM PDT 24
Peak memory 204252 kb
Host smart-d458faf4-a08e-4dee-8818-b4afbb0bd2a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054207717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1054207717
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3621158845
Short name T75
Test name
Test status
Simulation time 35195632 ps
CPU time 0.88 seconds
Started May 28 01:01:12 PM PDT 24
Finished May 28 01:01:14 PM PDT 24
Peak memory 204280 kb
Host smart-f904d0f2-35e4-442e-b87c-5faf9cb11c25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621158845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3621158845
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.4221705748
Short name T82
Test name
Test status
Simulation time 155805339 ps
CPU time 2.09 seconds
Started May 28 01:01:24 PM PDT 24
Finished May 28 01:01:28 PM PDT 24
Peak memory 204520 kb
Host smart-4771f92b-81ff-48e0-80b6-7d34b3d5f5d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221705748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.4221705748
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1681313927
Short name T153
Test name
Test status
Simulation time 138112292 ps
CPU time 2.3 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:24 PM PDT 24
Peak memory 204568 kb
Host smart-5ad3c93d-54ae-4f3f-95c9-37fe835e5711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681313927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1681313927
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2037026364
Short name T57
Test name
Test status
Simulation time 1738658180 ps
CPU time 1.86 seconds
Started May 28 01:01:08 PM PDT 24
Finished May 28 01:01:11 PM PDT 24
Peak memory 204508 kb
Host smart-321177f8-e312-40ed-9e9c-cfa3225513cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037026364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2037026364
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2749003902
Short name T121
Test name
Test status
Simulation time 40922059 ps
CPU time 1.06 seconds
Started May 28 01:01:08 PM PDT 24
Finished May 28 01:01:10 PM PDT 24
Peak memory 204536 kb
Host smart-68aae658-1b17-44ab-adf6-511e9e9a991a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749003902 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2749003902
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.421329821
Short name T156
Test name
Test status
Simulation time 25572484 ps
CPU time 0.75 seconds
Started May 28 01:00:57 PM PDT 24
Finished May 28 01:00:58 PM PDT 24
Peak memory 204316 kb
Host smart-058a6e85-3280-4db6-8d39-c43342ed7860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421329821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.421329821
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.851400107
Short name T67
Test name
Test status
Simulation time 17347730 ps
CPU time 0.65 seconds
Started May 28 01:00:58 PM PDT 24
Finished May 28 01:01:00 PM PDT 24
Peak memory 204168 kb
Host smart-d62874d2-68d5-418e-aa73-e0f8a5e7b3ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851400107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.851400107
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2726215782
Short name T73
Test name
Test status
Simulation time 57235051 ps
CPU time 0.88 seconds
Started May 28 01:01:14 PM PDT 24
Finished May 28 01:01:18 PM PDT 24
Peak memory 204292 kb
Host smart-001aae7a-9728-417d-864c-47bb6e42e45c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726215782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2726215782
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1175250252
Short name T115
Test name
Test status
Simulation time 1184538329 ps
CPU time 2.16 seconds
Started May 28 01:00:56 PM PDT 24
Finished May 28 01:00:59 PM PDT 24
Peak memory 204472 kb
Host smart-abcad020-2d0b-485c-bf7a-02b85ae5de8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175250252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1175250252
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2460529308
Short name T40
Test name
Test status
Simulation time 23610842 ps
CPU time 0.68 seconds
Started May 28 01:01:30 PM PDT 24
Finished May 28 01:01:33 PM PDT 24
Peak memory 204252 kb
Host smart-76701d97-9f07-4e99-a650-657c2e901ed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460529308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2460529308
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2630862601
Short name T113
Test name
Test status
Simulation time 42502585 ps
CPU time 0.7 seconds
Started May 28 01:01:25 PM PDT 24
Finished May 28 01:01:27 PM PDT 24
Peak memory 204252 kb
Host smart-b5d31b56-3282-4a6f-bcd7-f987a8a29b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630862601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2630862601
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1186815539
Short name T68
Test name
Test status
Simulation time 31917076 ps
CPU time 0.69 seconds
Started May 28 01:01:20 PM PDT 24
Finished May 28 01:01:27 PM PDT 24
Peak memory 204292 kb
Host smart-297fa178-4fc3-4c48-9b1d-cc7784799b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186815539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1186815539
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1285215848
Short name T63
Test name
Test status
Simulation time 23462632 ps
CPU time 0.72 seconds
Started May 28 01:01:22 PM PDT 24
Finished May 28 01:01:25 PM PDT 24
Peak memory 204216 kb
Host smart-fd994751-3a18-4b60-97c9-f17eb30da74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285215848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1285215848
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3417651624
Short name T145
Test name
Test status
Simulation time 169729391 ps
CPU time 0.73 seconds
Started May 28 01:01:28 PM PDT 24
Finished May 28 01:01:31 PM PDT 24
Peak memory 204196 kb
Host smart-912f6d4d-1ef8-4bce-81bf-02b13e0efd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417651624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3417651624
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.3981943713
Short name T128
Test name
Test status
Simulation time 51711224 ps
CPU time 0.67 seconds
Started May 28 01:01:27 PM PDT 24
Finished May 28 01:01:30 PM PDT 24
Peak memory 204252 kb
Host smart-d11e4894-69ef-41c2-971a-fc7aa9458a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981943713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3981943713
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3908759923
Short name T76
Test name
Test status
Simulation time 19417895 ps
CPU time 0.65 seconds
Started May 28 01:01:16 PM PDT 24
Finished May 28 01:01:19 PM PDT 24
Peak memory 204256 kb
Host smart-f27590c6-1f67-4182-b296-3a7a7be1dbae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908759923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3908759923
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2159145269
Short name T79
Test name
Test status
Simulation time 317499209 ps
CPU time 2.01 seconds
Started May 28 01:00:59 PM PDT 24
Finished May 28 01:01:01 PM PDT 24
Peak memory 204492 kb
Host smart-f33a2cfc-d1d2-457e-8f19-d3f0a3cb99bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159145269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2159145269
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.563647204
Short name T93
Test name
Test status
Simulation time 441702026 ps
CPU time 3.3 seconds
Started May 28 01:00:57 PM PDT 24
Finished May 28 01:01:01 PM PDT 24
Peak memory 204412 kb
Host smart-97f1b243-d432-4a41-b145-1f1084f94e00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563647204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.563647204
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1371007245
Short name T149
Test name
Test status
Simulation time 18955310 ps
CPU time 0.65 seconds
Started May 28 01:01:17 PM PDT 24
Finished May 28 01:01:20 PM PDT 24
Peak memory 204284 kb
Host smart-c8b24933-bd85-44c8-b0f2-e83abf0668ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371007245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1371007245
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1992207908
Short name T26
Test name
Test status
Simulation time 38952148 ps
CPU time 0.97 seconds
Started May 28 01:01:07 PM PDT 24
Finished May 28 01:01:09 PM PDT 24
Peak memory 204196 kb
Host smart-9e71c92a-b259-4f12-85b8-c3f5e0e3d993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992207908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1992207908
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3436059509
Short name T107
Test name
Test status
Simulation time 254355517 ps
CPU time 2.38 seconds
Started May 28 01:00:57 PM PDT 24
Finished May 28 01:01:00 PM PDT 24
Peak memory 204444 kb
Host smart-26d951f0-03ef-4a4c-8f1d-a7bc02c67e84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436059509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3436059509
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.663297262
Short name T89
Test name
Test status
Simulation time 46466604 ps
CPU time 0.65 seconds
Started May 28 01:01:36 PM PDT 24
Finished May 28 01:01:39 PM PDT 24
Peak memory 204324 kb
Host smart-4574844e-b8e4-4378-8b19-1f0a9803b71a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663297262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.663297262
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2745936753
Short name T39
Test name
Test status
Simulation time 22204646 ps
CPU time 0.67 seconds
Started May 28 01:01:17 PM PDT 24
Finished May 28 01:01:20 PM PDT 24
Peak memory 204188 kb
Host smart-9734afe6-4f1b-4d8a-a455-983cabe816ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745936753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2745936753
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.777866000
Short name T161
Test name
Test status
Simulation time 15861170 ps
CPU time 0.65 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:15 PM PDT 24
Peak memory 204164 kb
Host smart-a451d433-9aa0-4588-88fd-3f5f644bc15f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777866000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.777866000
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3846973592
Short name T119
Test name
Test status
Simulation time 18503145 ps
CPU time 0.68 seconds
Started May 28 01:01:23 PM PDT 24
Finished May 28 01:01:26 PM PDT 24
Peak memory 204256 kb
Host smart-71cfef2d-35f9-4582-b9fe-846805b0bead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846973592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3846973592
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.4196998791
Short name T66
Test name
Test status
Simulation time 17212074 ps
CPU time 0.68 seconds
Started May 28 01:01:12 PM PDT 24
Finished May 28 01:01:15 PM PDT 24
Peak memory 204168 kb
Host smart-585595e5-4e35-4a18-8753-6a724bdd8022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196998791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.4196998791
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2733925306
Short name T15
Test name
Test status
Simulation time 26301910 ps
CPU time 0.67 seconds
Started May 28 01:01:21 PM PDT 24
Finished May 28 01:01:25 PM PDT 24
Peak memory 204304 kb
Host smart-41cdf46e-92a1-402b-bcc2-cc7331feeed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733925306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2733925306
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.602281750
Short name T65
Test name
Test status
Simulation time 16736374 ps
CPU time 0.66 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204128 kb
Host smart-0eced2c8-87a9-45e1-838b-e5dc89323037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602281750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.602281750
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.4221699874
Short name T43
Test name
Test status
Simulation time 28600809 ps
CPU time 0.69 seconds
Started May 28 01:01:15 PM PDT 24
Finished May 28 01:01:18 PM PDT 24
Peak memory 204304 kb
Host smart-ea517f9f-d2ff-439c-91f2-87f267d8391b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221699874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.4221699874
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1311535524
Short name T159
Test name
Test status
Simulation time 18822055 ps
CPU time 0.73 seconds
Started May 28 01:01:25 PM PDT 24
Finished May 28 01:01:28 PM PDT 24
Peak memory 204252 kb
Host smart-19872801-e872-4721-9542-c9e6afc5f264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311535524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1311535524
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.484821390
Short name T35
Test name
Test status
Simulation time 265789558 ps
CPU time 2.38 seconds
Started May 28 01:00:51 PM PDT 24
Finished May 28 01:00:54 PM PDT 24
Peak memory 204508 kb
Host smart-36c80132-5688-474d-bacc-c559857a0e65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484821390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.484821390
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3378166907
Short name T147
Test name
Test status
Simulation time 448572655 ps
CPU time 3.23 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:25 PM PDT 24
Peak memory 204532 kb
Host smart-e5f9e423-cb2e-4836-806d-12ef617ec2e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378166907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3378166907
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1512221716
Short name T60
Test name
Test status
Simulation time 19483767 ps
CPU time 0.69 seconds
Started May 28 01:01:04 PM PDT 24
Finished May 28 01:01:06 PM PDT 24
Peak memory 204180 kb
Host smart-c92ac4bb-09d9-43e9-bfd1-4f7766d57f41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512221716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1512221716
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.373038999
Short name T4
Test name
Test status
Simulation time 45234872 ps
CPU time 1.14 seconds
Started May 28 01:01:10 PM PDT 24
Finished May 28 01:01:12 PM PDT 24
Peak memory 204488 kb
Host smart-57fef674-72b9-44a3-b090-8d9bd642040b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373038999 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.373038999
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2180985265
Short name T31
Test name
Test status
Simulation time 26424358 ps
CPU time 0.82 seconds
Started May 28 01:01:04 PM PDT 24
Finished May 28 01:01:06 PM PDT 24
Peak memory 204268 kb
Host smart-b7eedcd6-8a85-4ac9-978f-a640b7c823ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180985265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2180985265
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.811896425
Short name T152
Test name
Test status
Simulation time 16948495 ps
CPU time 0.64 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:22 PM PDT 24
Peak memory 204264 kb
Host smart-8e2af96b-f0cd-4a0c-b8e1-c8635f8c81ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811896425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.811896425
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2271138146
Short name T129
Test name
Test status
Simulation time 40346843 ps
CPU time 0.92 seconds
Started May 28 01:01:19 PM PDT 24
Finished May 28 01:01:27 PM PDT 24
Peak memory 204292 kb
Host smart-dcbfce60-d2be-4312-aa76-44ddd7e4f49a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271138146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2271138146
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1010353492
Short name T95
Test name
Test status
Simulation time 246391808 ps
CPU time 1.76 seconds
Started May 28 01:01:07 PM PDT 24
Finished May 28 01:01:09 PM PDT 24
Peak memory 204528 kb
Host smart-746674cd-00df-472f-b188-6ae310ee404a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010353492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1010353492
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.876212804
Short name T127
Test name
Test status
Simulation time 54990896 ps
CPU time 0.73 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:21 PM PDT 24
Peak memory 204248 kb
Host smart-b30f2812-3203-4c8b-a640-3c68742e8bba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876212804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.876212804
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3668403243
Short name T137
Test name
Test status
Simulation time 15364552 ps
CPU time 0.68 seconds
Started May 28 01:01:34 PM PDT 24
Finished May 28 01:01:36 PM PDT 24
Peak memory 204332 kb
Host smart-de3e4bdc-60ae-4e97-b7cf-51fd0ca2733b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668403243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3668403243
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2398979360
Short name T146
Test name
Test status
Simulation time 39279986 ps
CPU time 0.69 seconds
Started May 28 01:01:09 PM PDT 24
Finished May 28 01:01:11 PM PDT 24
Peak memory 204264 kb
Host smart-410856c6-e819-4c3c-be8f-f2e7005eff26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398979360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2398979360
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2649340266
Short name T13
Test name
Test status
Simulation time 22783895 ps
CPU time 0.63 seconds
Started May 28 01:01:14 PM PDT 24
Finished May 28 01:01:17 PM PDT 24
Peak memory 204252 kb
Host smart-5bbf567b-bc4b-40cc-8115-a10382fae841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649340266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2649340266
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.472334977
Short name T134
Test name
Test status
Simulation time 23392329 ps
CPU time 0.67 seconds
Started May 28 01:01:12 PM PDT 24
Finished May 28 01:01:14 PM PDT 24
Peak memory 204260 kb
Host smart-f621440a-9bef-4791-b3f5-bd7fcaab8c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472334977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.472334977
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2117628495
Short name T131
Test name
Test status
Simulation time 23646954 ps
CPU time 0.65 seconds
Started May 28 01:01:30 PM PDT 24
Finished May 28 01:01:33 PM PDT 24
Peak memory 204252 kb
Host smart-4279753b-a382-44ab-8ec6-8eaf6aaac280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117628495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2117628495
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1789179407
Short name T136
Test name
Test status
Simulation time 29873407 ps
CPU time 0.69 seconds
Started May 28 01:01:11 PM PDT 24
Finished May 28 01:01:13 PM PDT 24
Peak memory 204200 kb
Host smart-836cdd57-d02e-41c6-a96c-f28c78c99972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789179407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1789179407
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.583319053
Short name T122
Test name
Test status
Simulation time 43187457 ps
CPU time 0.65 seconds
Started May 28 01:01:15 PM PDT 24
Finished May 28 01:01:18 PM PDT 24
Peak memory 204260 kb
Host smart-bca26e82-08f5-4285-ada6-65fea805ac87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583319053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.583319053
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2655488105
Short name T133
Test name
Test status
Simulation time 22028799 ps
CPU time 0.69 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204284 kb
Host smart-274b0791-9e3f-4207-a24e-6b2611fd0546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655488105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2655488105
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2001571911
Short name T86
Test name
Test status
Simulation time 25669866 ps
CPU time 0.64 seconds
Started May 28 01:01:18 PM PDT 24
Finished May 28 01:01:21 PM PDT 24
Peak memory 204132 kb
Host smart-270f5fe8-9559-4d81-9fc1-401705d6cc74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001571911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2001571911
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.171950658
Short name T81
Test name
Test status
Simulation time 78789002 ps
CPU time 0.86 seconds
Started May 28 01:01:16 PM PDT 24
Finished May 28 01:01:20 PM PDT 24
Peak memory 204360 kb
Host smart-94010ee3-f39b-4623-9615-3167550715c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171950658 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.171950658
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3114253321
Short name T38
Test name
Test status
Simulation time 26092553 ps
CPU time 0.81 seconds
Started May 28 01:01:00 PM PDT 24
Finished May 28 01:01:01 PM PDT 24
Peak memory 204112 kb
Host smart-e3dcfc98-0e8d-4e55-862a-e6f99bef46d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114253321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3114253321
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2716788952
Short name T69
Test name
Test status
Simulation time 15874047 ps
CPU time 0.65 seconds
Started May 28 01:01:19 PM PDT 24
Finished May 28 01:01:23 PM PDT 24
Peak memory 204232 kb
Host smart-b114746d-329d-447a-a73e-81af6e7217ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716788952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2716788952
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.718532518
Short name T21
Test name
Test status
Simulation time 50613402 ps
CPU time 1.12 seconds
Started May 28 01:00:57 PM PDT 24
Finished May 28 01:00:59 PM PDT 24
Peak memory 204512 kb
Host smart-c3180eee-d270-476c-bce6-057ec90de003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718532518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_out
standing.718532518
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2347139510
Short name T142
Test name
Test status
Simulation time 500223894 ps
CPU time 2.55 seconds
Started May 28 01:01:15 PM PDT 24
Finished May 28 01:01:20 PM PDT 24
Peak memory 204648 kb
Host smart-4405e761-3776-4c87-9526-6b8b456c8552
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347139510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2347139510
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3937556994
Short name T10
Test name
Test status
Simulation time 313609725 ps
CPU time 1.55 seconds
Started May 28 01:00:50 PM PDT 24
Finished May 28 01:00:52 PM PDT 24
Peak memory 204452 kb
Host smart-2ea77ba7-fb60-4830-ae61-0adc7c755628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937556994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3937556994
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2596419841
Short name T6
Test name
Test status
Simulation time 116055724 ps
CPU time 0.99 seconds
Started May 28 01:01:15 PM PDT 24
Finished May 28 01:01:18 PM PDT 24
Peak memory 204452 kb
Host smart-1f5d38f1-4310-44c7-91a3-eed842eefb0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596419841 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2596419841
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1237595718
Short name T112
Test name
Test status
Simulation time 53401170 ps
CPU time 0.73 seconds
Started May 28 01:01:06 PM PDT 24
Finished May 28 01:01:08 PM PDT 24
Peak memory 204248 kb
Host smart-2eba276e-7c16-4a19-af39-888681eb7567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237595718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1237595718
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.83576843
Short name T103
Test name
Test status
Simulation time 46543938 ps
CPU time 0.66 seconds
Started May 28 01:00:55 PM PDT 24
Finished May 28 01:00:56 PM PDT 24
Peak memory 204152 kb
Host smart-5ec50806-22af-489d-945a-cd7434c400f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83576843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.83576843
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4129405685
Short name T84
Test name
Test status
Simulation time 152534870 ps
CPU time 1.2 seconds
Started May 28 01:01:04 PM PDT 24
Finished May 28 01:01:06 PM PDT 24
Peak memory 204432 kb
Host smart-4d949af9-43d5-47d5-bd0a-32fb0449e901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129405685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.4129405685
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3956711355
Short name T111
Test name
Test status
Simulation time 56481146 ps
CPU time 2.59 seconds
Started May 28 01:01:19 PM PDT 24
Finished May 28 01:01:25 PM PDT 24
Peak memory 204416 kb
Host smart-cc88499d-5f96-43d2-8677-0f8d6f41c08a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956711355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3956711355
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2909806168
Short name T88
Test name
Test status
Simulation time 129182552 ps
CPU time 0.96 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204388 kb
Host smart-977a129f-1954-4bc3-8c73-f58fa1b0990f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909806168 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2909806168
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3906303335
Short name T141
Test name
Test status
Simulation time 33913136 ps
CPU time 0.76 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204220 kb
Host smart-2b636a61-f37a-43bc-9e87-e2d34eeea7d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906303335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3906303335
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2389964821
Short name T97
Test name
Test status
Simulation time 138302643 ps
CPU time 0.66 seconds
Started May 28 01:01:02 PM PDT 24
Finished May 28 01:01:04 PM PDT 24
Peak memory 204160 kb
Host smart-29868f24-394f-495f-87ac-bc13cf87b38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389964821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2389964821
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3753685323
Short name T130
Test name
Test status
Simulation time 23852961 ps
CPU time 0.9 seconds
Started May 28 01:01:21 PM PDT 24
Finished May 28 01:01:25 PM PDT 24
Peak memory 204360 kb
Host smart-3d0646d2-46fe-43ea-b2df-abfbc4174a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753685323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3753685323
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2449919958
Short name T144
Test name
Test status
Simulation time 110226212 ps
CPU time 1.58 seconds
Started May 28 01:01:11 PM PDT 24
Finished May 28 01:01:14 PM PDT 24
Peak memory 204416 kb
Host smart-040392c9-307f-4bd8-af5f-1c0b917a4b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449919958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2449919958
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3178736971
Short name T151
Test name
Test status
Simulation time 277667462 ps
CPU time 2.22 seconds
Started May 28 01:01:06 PM PDT 24
Finished May 28 01:01:09 PM PDT 24
Peak memory 204564 kb
Host smart-8679e6fd-2363-4388-b39c-3c319327801b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178736971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3178736971
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2886159283
Short name T98
Test name
Test status
Simulation time 43007450 ps
CPU time 0.81 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204328 kb
Host smart-d52733fd-ef36-45de-b6cb-031de2498168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886159283 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2886159283
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1100830979
Short name T101
Test name
Test status
Simulation time 16823112 ps
CPU time 0.78 seconds
Started May 28 01:01:15 PM PDT 24
Finished May 28 01:01:18 PM PDT 24
Peak memory 204232 kb
Host smart-13849a66-4c5f-4f2b-98eb-2be8e6c0a541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100830979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1100830979
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.2419718083
Short name T106
Test name
Test status
Simulation time 27938580 ps
CPU time 0.63 seconds
Started May 28 01:00:56 PM PDT 24
Finished May 28 01:00:58 PM PDT 24
Peak memory 204184 kb
Host smart-03206fec-40a2-44cd-9444-8dcd156904bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419718083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2419718083
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4016098992
Short name T105
Test name
Test status
Simulation time 38499168 ps
CPU time 0.96 seconds
Started May 28 01:00:58 PM PDT 24
Finished May 28 01:01:00 PM PDT 24
Peak memory 204392 kb
Host smart-c79159bb-1ab7-4298-9662-0049226b4607
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016098992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.4016098992
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3079301463
Short name T16
Test name
Test status
Simulation time 25504787 ps
CPU time 1.12 seconds
Started May 28 01:01:09 PM PDT 24
Finished May 28 01:01:11 PM PDT 24
Peak memory 204288 kb
Host smart-2b47a327-ae4b-4483-bcb3-4817c0ef7e24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079301463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3079301463
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2507700041
Short name T49
Test name
Test status
Simulation time 160060816 ps
CPU time 1.53 seconds
Started May 28 01:01:07 PM PDT 24
Finished May 28 01:01:09 PM PDT 24
Peak memory 204564 kb
Host smart-7a42f9cf-be1c-4d35-921c-48f54c0423c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507700041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2507700041
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1697615256
Short name T155
Test name
Test status
Simulation time 29804810 ps
CPU time 1.37 seconds
Started May 28 01:01:06 PM PDT 24
Finished May 28 01:01:08 PM PDT 24
Peak memory 212832 kb
Host smart-24941f47-7422-4ebf-a9c2-0c6252ce50f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697615256 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1697615256
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.219334161
Short name T22
Test name
Test status
Simulation time 40032879 ps
CPU time 0.79 seconds
Started May 28 01:01:17 PM PDT 24
Finished May 28 01:01:23 PM PDT 24
Peak memory 204232 kb
Host smart-40958cd8-3949-48c4-9dfd-19cf5d533190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219334161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.219334161
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1391946638
Short name T139
Test name
Test status
Simulation time 115535173 ps
CPU time 0.65 seconds
Started May 28 01:01:13 PM PDT 24
Finished May 28 01:01:16 PM PDT 24
Peak memory 204248 kb
Host smart-bd6dc238-15cc-49a2-aecd-a6f7a90f5239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391946638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1391946638
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.850741480
Short name T36
Test name
Test status
Simulation time 58606594 ps
CPU time 0.9 seconds
Started May 28 01:01:07 PM PDT 24
Finished May 28 01:01:08 PM PDT 24
Peak memory 204240 kb
Host smart-f0fcaf2a-8960-41d0-8db2-e9b5bcbf8d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850741480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out
standing.850741480
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.510264505
Short name T80
Test name
Test status
Simulation time 136301826 ps
CPU time 2.01 seconds
Started May 28 01:01:03 PM PDT 24
Finished May 28 01:01:06 PM PDT 24
Peak memory 204564 kb
Host smart-37b26c90-bf37-4bb7-937f-98e4f67a7398
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510264505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.510264505
Directory /workspace/9.i2c_tl_errors/latest
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