Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	334	1			T1	8		T2	1		T3	1
all_pins[1]	334	1			T1	8		T2	1		T3	1
all_pins[2]	334	1			T1	8		T2	1		T3	1
all_pins[3]	334	1			T1	8		T2	1		T3	1
all_pins[4]	334	1			T1	8		T2	1		T3	1
all_pins[5]	334	1			T1	8		T2	1		T3	1
all_pins[6]	334	1			T1	8		T2	1		T3	1
all_pins[7]	334	1			T1	8		T2	1		T3	1
all_pins[8]	334	1			T1	8		T2	1		T3	1
all_pins[9]	334	1			T1	8		T2	1		T3	1
all_pins[10]	334	1			T1	8		T2	1		T3	1
all_pins[11]	334	1			T1	8		T2	1		T3	1
all_pins[12]	334	1			T1	8		T2	1		T3	1
all_pins[13]	334	1			T1	8		T2	1		T3	1
all_pins[14]	334	1			T1	8		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4150	1			T1	94		T2	15		T3	15
values[0x1]	860	1			T1	26		T12	28		T7	25
transitions[0x0=>0x1]	647	1			T1	20		T12	15		T7	16
transitions[0x1=>0x0]	655	1			T1	20		T12	16		T7	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	282	1			T1	6		T2	1		T3	1
all_pins[0]	values[0x1]	52	1			T1	2		T7	3		T15	2
all_pins[0]	transitions[0x0=>0x1]	40	1			T1	2		T7	3		T39	1
all_pins[0]	transitions[0x1=>0x0]	50	1			T1	2		T12	2		T7	1
all_pins[1]	values[0x0]	272	1			T1	6		T2	1		T3	1
all_pins[1]	values[0x1]	62	1			T1	2		T12	2		T7	1
all_pins[1]	transitions[0x0=>0x1]	46	1			T12	2		T13	1		T15	1
all_pins[1]	transitions[0x1=>0x0]	46	1			T1	3		T12	1		T7	1
all_pins[2]	values[0x0]	272	1			T1	3		T2	1		T3	1
all_pins[2]	values[0x1]	62	1			T1	5		T12	1		T7	2
all_pins[2]	transitions[0x0=>0x1]	51	1			T1	5		T12	1		T7	2
all_pins[2]	transitions[0x1=>0x0]	42	1			T7	2		T13	3		T15	2
all_pins[3]	values[0x0]	281	1			T1	8		T2	1		T3	1
all_pins[3]	values[0x1]	53	1			T7	2		T13	3		T15	2
all_pins[3]	transitions[0x0=>0x1]	41	1			T7	1		T13	2		T15	2
all_pins[3]	transitions[0x1=>0x0]	40	1			T12	2		T7	1		T43	2
all_pins[4]	values[0x0]	282	1			T1	8		T2	1		T3	1
all_pins[4]	values[0x1]	52	1			T12	2		T7	2		T13	1
all_pins[4]	transitions[0x0=>0x1]	37	1			T12	1		T7	2		T40	1
all_pins[4]	transitions[0x1=>0x0]	44	1			T1	2		T12	2		T13	1
all_pins[5]	values[0x0]	275	1			T1	6		T2	1		T3	1
all_pins[5]	values[0x1]	59	1			T1	2		T12	3		T13	2
all_pins[5]	transitions[0x0=>0x1]	37	1			T1	2		T13	2		T14	3
all_pins[5]	transitions[0x1=>0x0]	53	1			T12	3		T7	2		T14	1
all_pins[6]	values[0x0]	259	1			T1	8		T2	1		T3	1
all_pins[6]	values[0x1]	75	1			T12	6		T7	2		T14	1
all_pins[6]	transitions[0x0=>0x1]	61	1			T12	3		T40	1		T61	1
all_pins[6]	transitions[0x1=>0x0]	29	1			T15	2		T14	2		T62	2
all_pins[7]	values[0x0]	291	1			T1	8		T2	1		T3	1
all_pins[7]	values[0x1]	43	1			T12	3		T7	2		T15	2
all_pins[7]	transitions[0x0=>0x1]	29	1			T12	1		T7	2		T14	2
all_pins[7]	transitions[0x1=>0x0]	47	1			T1	4		T39	1		T61	1
all_pins[8]	values[0x0]	273	1			T1	4		T2	1		T3	1
all_pins[8]	values[0x1]	61	1			T1	4		T12	2		T15	2
all_pins[8]	transitions[0x0=>0x1]	46	1			T1	1		T12	1		T15	2
all_pins[8]	transitions[0x1=>0x0]	46	1			T1	1		T12	1		T7	1
all_pins[9]	values[0x0]	273	1			T1	4		T2	1		T3	1
all_pins[9]	values[0x1]	61	1			T1	4		T12	2		T7	1
all_pins[9]	transitions[0x0=>0x1]	50	1			T1	4		T7	1		T14	2
all_pins[9]	transitions[0x1=>0x0]	38	1			T1	1		T12	1		T15	2
all_pins[10]	values[0x0]	285	1			T1	7		T2	1		T3	1
all_pins[10]	values[0x1]	49	1			T1	1		T12	3		T15	2
all_pins[10]	transitions[0x0=>0x1]	36	1			T1	1		T12	3		T15	1
all_pins[10]	transitions[0x1=>0x0]	48	1			T1	3		T12	1		T7	1
all_pins[11]	values[0x0]	273	1			T1	5		T2	1		T3	1
all_pins[11]	values[0x1]	61	1			T1	3		T12	1		T7	1
all_pins[11]	transitions[0x0=>0x1]	48	1			T1	2		T12	1		T13	2
all_pins[11]	transitions[0x1=>0x0]	43	1			T1	1		T12	1		T7	3
all_pins[12]	values[0x0]	278	1			T1	6		T2	1		T3	1
all_pins[12]	values[0x1]	56	1			T1	2		T12	1		T7	4
all_pins[12]	transitions[0x0=>0x1]	42	1			T1	2		T12	1		T15	1
all_pins[12]	transitions[0x1=>0x0]	47	1			T7	1		T13	1		T40	2
all_pins[13]	values[0x0]	273	1			T1	8		T2	1		T3	1
all_pins[13]	values[0x1]	61	1			T7	5		T13	1		T40	2
all_pins[13]	transitions[0x0=>0x1]	51	1			T7	5		T13	1		T40	2
all_pins[13]	transitions[0x1=>0x0]	43	1			T1	1		T12	2		T13	1
all_pins[14]	values[0x0]	281	1			T1	7		T2	1		T3	1
all_pins[14]	values[0x1]	53	1			T1	1		T12	2		T13	1
all_pins[14]	transitions[0x0=>0x1]	32	1			T1	1		T12	1		T13	1
all_pins[14]	transitions[0x1=>0x0]	39	1			T1	2		T7	3		T15	2