Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T1	7		T12	7		T7	7
all_values[1]	266	1			T1	7		T12	7		T7	7
all_values[2]	266	1			T1	7		T12	7		T7	7
all_values[3]	266	1			T1	7		T12	7		T7	7
all_values[4]	266	1			T1	7		T12	7		T7	7
all_values[5]	266	1			T1	7		T12	7		T7	7
all_values[6]	266	1			T1	7		T12	7		T7	7
all_values[7]	266	1			T1	7		T12	7		T7	7
all_values[8]	266	1			T1	7		T12	7		T7	7
all_values[9]	266	1			T1	7		T12	7		T7	7
all_values[10]	266	1			T1	7		T12	7		T7	7
all_values[11]	266	1			T1	7		T12	7		T7	7
all_values[12]	266	1			T1	7		T12	7		T7	7
all_values[13]	266	1			T1	7		T12	7		T7	7
all_values[14]	266	1			T1	7		T12	7		T7	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2194

1

T1

53

T12

60

T7

54

auto[1]

1796

1

T1

52

T12

45

T7

51

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

722

1

T1

8

T12

10

T7

16

auto[1]

3268

1

T1

97

T12

95

T7

89

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2380

1

T1

55

T12

50

T7

56

auto[1]

1610

1

T1

50

T12

55

T7

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1			T1	1		T12	7		T63	3
all_values[0]	auto[0]	auto[0]	auto[1]	65	1			T1	1		T7	1		T14	2
all_values[0]	auto[0]	auto[1]	auto[0]	20	1			T13	4		T39	1		T64	2
all_values[0]	auto[0]	auto[1]	auto[1]	48	1			T1	1		T7	1		T15	1
all_values[0]	auto[1]	auto[0]	auto[1]	59	1			T1	2		T7	3		T15	1
all_values[0]	auto[1]	auto[1]	auto[1]	44	1			T1	2		T7	2		T15	2
all_values[1]	auto[0]	auto[0]	auto[0]	19	1			T7	2		T13	1		T40	1
all_values[1]	auto[0]	auto[0]	auto[1]	55	1			T1	2		T14	2		T40	1
all_values[1]	auto[0]	auto[1]	auto[0]	20	1			T61	1		T65	3		T64	3
all_values[1]	auto[0]	auto[1]	auto[1]	66	1			T1	2		T12	4		T7	3
all_values[1]	auto[1]	auto[0]	auto[1]	55	1			T1	1		T12	3		T13	1
all_values[1]	auto[1]	auto[1]	auto[1]	51	1			T1	2		T7	2		T15	2
all_values[2]	auto[0]	auto[0]	auto[0]	23	1			T12	1		T61	1		T66	1
all_values[2]	auto[0]	auto[0]	auto[1]	63	1			T12	2		T7	4		T15	1
all_values[2]	auto[0]	auto[1]	auto[0]	16	1			T39	2		T62	2		T61	1
all_values[2]	auto[0]	auto[1]	auto[1]	48	1			T1	2		T13	2		T15	2
all_values[2]	auto[1]	auto[0]	auto[1]	60	1			T1	1		T12	4		T7	2
all_values[2]	auto[1]	auto[1]	auto[1]	56	1			T1	4		T7	1		T13	2
all_values[3]	auto[0]	auto[0]	auto[0]	48	1			T7	1		T13	1		T39	2
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T12	1		T7	1		T14	1
all_values[3]	auto[0]	auto[1]	auto[0]	16	1			T7	2		T15	2		T65	1
all_values[3]	auto[0]	auto[1]	auto[1]	48	1			T1	4		T12	2		T7	1
all_values[3]	auto[1]	auto[0]	auto[1]	57	1			T1	3		T12	3		T7	1
all_values[3]	auto[1]	auto[1]	auto[1]	40	1			T12	1		T7	1		T40	2
all_values[4]	auto[0]	auto[0]	auto[0]	27	1			T7	1		T13	1		T43	1
all_values[4]	auto[0]	auto[0]	auto[1]	50	1			T1	2		T15	1		T14	1
all_values[4]	auto[0]	auto[1]	auto[0]	14	1			T15	2		T40	1		T62	1
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T1	3		T12	3		T7	2
all_values[4]	auto[1]	auto[0]	auto[1]	60	1			T1	1		T12	3		T7	3
all_values[4]	auto[1]	auto[1]	auto[1]	47	1			T1	1		T12	1		T7	1
all_values[5]	auto[0]	auto[0]	auto[0]	20	1			T15	1		T43	1		T63	1
all_values[5]	auto[0]	auto[0]	auto[1]	45	1			T1	1		T12	1		T13	1
all_values[5]	auto[0]	auto[1]	auto[0]	21	1			T15	3		T39	1		T65	3
all_values[5]	auto[0]	auto[1]	auto[1]	51	1			T1	3		T12	1		T7	4
all_values[5]	auto[1]	auto[0]	auto[1]	72	1			T1	1		T12	1		T7	2
all_values[5]	auto[1]	auto[1]	auto[1]	57	1			T1	2		T12	4		T7	1
all_values[6]	auto[0]	auto[0]	auto[0]	25	1			T13	1		T15	1		T61	1
all_values[6]	auto[0]	auto[0]	auto[1]	60	1			T1	2		T13	2		T15	2
all_values[6]	auto[0]	auto[1]	auto[0]	16	1			T39	2		T62	1		T67	2
all_values[6]	auto[0]	auto[1]	auto[1]	62	1			T12	2		T7	4		T14	2
all_values[6]	auto[1]	auto[0]	auto[1]	55	1			T1	5		T12	1		T7	2
all_values[6]	auto[1]	auto[1]	auto[1]	48	1			T12	4		T7	1		T14	1
all_values[7]	auto[0]	auto[0]	auto[0]	35	1			T1	2		T7	1		T40	2
all_values[7]	auto[0]	auto[0]	auto[1]	64	1			T1	3		T12	4		T13	1
all_values[7]	auto[0]	auto[1]	auto[0]	15	1			T7	1		T13	1		T15	1
all_values[7]	auto[0]	auto[1]	auto[1]	51	1			T7	2		T15	1		T14	1
all_values[7]	auto[1]	auto[0]	auto[1]	60	1			T1	2		T12	2		T13	1
all_values[7]	auto[1]	auto[1]	auto[1]	41	1			T12	1		T7	3		T13	1
all_values[8]	auto[0]	auto[0]	auto[0]	31	1			T12	1		T7	1		T13	4
all_values[8]	auto[0]	auto[0]	auto[1]	57	1			T7	3		T14	3		T39	1
all_values[8]	auto[0]	auto[1]	auto[0]	23	1			T7	1		T15	1		T39	1
all_values[8]	auto[0]	auto[1]	auto[1]	40	1			T1	3		T12	2		T15	1
all_values[8]	auto[1]	auto[0]	auto[1]	63	1			T1	2		T12	2		T7	2
all_values[8]	auto[1]	auto[1]	auto[1]	52	1			T1	2		T12	2		T15	2
all_values[9]	auto[0]	auto[0]	auto[0]	29	1			T1	1		T13	4		T14	2
all_values[9]	auto[0]	auto[0]	auto[1]	50	1			T12	1		T7	2		T15	2
all_values[9]	auto[0]	auto[1]	auto[0]	23	1			T40	2		T61	1		T68	1
all_values[9]	auto[0]	auto[1]	auto[1]	54	1			T1	2		T12	2		T7	1
all_values[9]	auto[1]	auto[0]	auto[1]	51	1			T1	1		T12	2		T7	4
all_values[9]	auto[1]	auto[1]	auto[1]	59	1			T1	3		T12	2		T61	2
all_values[10]	auto[0]	auto[0]	auto[0]	23	1			T12	1		T13	2		T39	4
all_values[10]	auto[0]	auto[0]	auto[1]	66	1			T7	2		T14	2		T40	2
all_values[10]	auto[0]	auto[1]	auto[0]	20	1			T13	2		T69	3		T67	2
all_values[10]	auto[0]	auto[1]	auto[1]	59	1			T1	4		T12	3		T7	1
all_values[10]	auto[1]	auto[0]	auto[1]	63	1			T1	3		T7	4		T15	1
all_values[10]	auto[1]	auto[1]	auto[1]	35	1			T12	3		T15	2		T14	1
all_values[11]	auto[0]	auto[0]	auto[0]	33	1			T7	1		T13	1		T15	2
all_values[11]	auto[0]	auto[0]	auto[1]	41	1			T1	1		T12	1		T14	1
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T7	2		T39	4		T63	3
all_values[11]	auto[0]	auto[1]	auto[1]	59	1			T1	1		T12	2		T7	2
all_values[11]	auto[1]	auto[0]	auto[1]	66	1			T1	3		T12	3		T7	2
all_values[11]	auto[1]	auto[1]	auto[1]	46	1			T1	2		T12	1		T13	1
all_values[12]	auto[0]	auto[0]	auto[0]	28	1			T1	1		T7	1		T15	1
all_values[12]	auto[0]	auto[0]	auto[1]	58	1			T1	2		T12	2		T14	1
all_values[12]	auto[0]	auto[1]	auto[0]	19	1			T13	4		T43	5		T64	1
all_values[12]	auto[0]	auto[1]	auto[1]	55	1			T1	1		T12	2		T7	1
all_values[12]	auto[1]	auto[0]	auto[1]	62	1			T1	1		T12	2		T7	1
all_values[12]	auto[1]	auto[1]	auto[1]	44	1			T1	2		T12	1		T7	4
all_values[13]	auto[0]	auto[0]	auto[0]	30	1			T7	1		T14	3		T39	3
all_values[13]	auto[0]	auto[0]	auto[1]	60	1			T1	4		T12	2		T13	1
all_values[13]	auto[0]	auto[1]	auto[0]	16	1			T14	1		T39	1		T61	2
all_values[13]	auto[0]	auto[1]	auto[1]	50	1			T1	1		T12	1		T7	1
all_values[13]	auto[1]	auto[0]	auto[1]	59	1			T1	1		T12	4		T13	1
all_values[13]	auto[1]	auto[1]	auto[1]	51	1			T1	1		T7	5		T13	1
all_values[14]	auto[0]	auto[0]	auto[0]	37	1			T1	1		T7	1		T40	2
all_values[14]	auto[0]	auto[0]	auto[1]	63	1			T1	1		T12	1		T7	4
all_values[14]	auto[0]	auto[1]	auto[0]	24	1			T1	2		T13	1		T39	2
all_values[14]	auto[0]	auto[1]	auto[1]	45	1			T1	1		T12	1		T13	2
all_values[14]	auto[1]	auto[0]	auto[1]	60	1			T1	1		T12	5		T7	1
all_values[14]	auto[1]	auto[1]	auto[1]	37	1			T1	1		T7	1		T13	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal