Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

167442

1

T3

103

T16

619

T31

23

ack

14439

1

T3

11

T10

47

T16

13

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	717	1			T3	2		T16	2		T63	1
high	37329	1			T3	36		T10	6		T16	120
med	67564	1			T3	35		T10	8		T16	242
sml	75565	1			T3	41		T10	33		T16	267
all_zero	706	1			T16	1		T33	1		T76	5

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90674

1

T3

54

T10

23

T16

315

auto[1]

91207

1

T3

60

T10

24

T16

317

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124741

1

T3

79

T10

35

T16

405

auto[1]

57140

1

T3

35

T10

12

T16

227

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174303

1

T3

114

T10

18

T16

619

auto[1]

7578

1

T10

29

T16

13

T31

6

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171879

1

T3

103

T10

29

T16

619

auto[1]

10002

1

T3

11

T10

18

T16

13

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172877

1

T3

103

T10

30

T16

622

auto[1]

9004

1

T3

11

T10

17

T16

10

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90674

1

T3

54

T10

23

T16

315

auto[1]

91207

1

T3

60

T10

24

T16

317

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124741

1

T3

79

T10

35

T16

405

auto[1]

57140

1

T3

35

T10

12

T16

227

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174303

1

T3

114

T10

18

T16

619

auto[1]

7578

1

T10

29

T16

13

T31

6

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171879

1

T3

103

T10

29

T16

619

auto[1]

10002

1

T3

11

T10

18

T16

13

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172877

1

T3

103

T10

30

T16

622

auto[1]

9004

1

T3

11

T10

17

T16

10

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

2

1

T240

1

T117

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T142

1

T111

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T241

1

T242

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

289

1

T33

2

T76

3

T39

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

146

1

T76

1

T93

1

T154

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

152

1

T16

3

T93

1

T153

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

556

1

T16

1

T31

1

T33

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

267

1

T16

2

T33

2

T76

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

262

1

T31

1

T76

2

T39

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

569

1

T16

2

T33

1

T76

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

281

1

T16

1

T33

3

T39

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

238

1

T16

1

T31

1

T33

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

8

1

T47

1

T45

1

T108

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T51

1

T243

1

T125

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T53

1

-

-

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	53327	1			T3	29		T16	179		T31	5
write_address_byte	10002	1			T3	11		T10	18		T16	13
read_with_ack	2192	1			T10	12		T16	7		T32	1
read_with_nack	5386	1			T10	17		T16	6		T31	6
stop_byte	9004	1			T3	11		T10	17		T16	10
write_address_byte_nak	5080	1			T16	12		T31	8		T32	4
data_byte_nack	167442	1			T3	103		T16	619		T31	23
stop_byte_nack	5520	1			T3	11		T16	10		T31	4
nakok_byte_nack	83992	1			T3	55		T16	308		T31	9
nakok_addr_byte_nack	2585	1			T16	7		T31	5		T32	1