Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42143034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10655807

1

T1

14

T2

161

T3

1713

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51852288	1			T1	13		T2	28809		T3	3427
values[0x0]	472291	1			T1	8		T2	101		T3	103
values[0x1]	474262	1			T1	8		T2	110		T3	99

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30075558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22723283

1

T1

17

T2

12679

T3

2137

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	182168	1			T3	12		T5	3		T6	5
valid_sources[0x01]	171675	1			T3	23		T5	2		T6	5
valid_sources[0x02]	177984	1			T3	14		T5	1		T8	3
valid_sources[0x03]	182685	1			T3	14		T4	28		T6	3
valid_sources[0x04]	191721	1			T3	13		T5	1		T6	2
valid_sources[0x05]	188444	1			T3	20		T6	5		T8	6
valid_sources[0x06]	181794	1			T3	12		T5	3		T6	5
valid_sources[0x07]	201432	1			T3	14		T4	6		T6	2
valid_sources[0x08]	184912	1			T3	15		T4	3		T6	4
valid_sources[0x09]	200841	1			T3	8		T5	2		T6	4
valid_sources[0x0a]	183516	1			T3	21		T6	4		T8	1
valid_sources[0x0b]	193571	1			T3	5		T4	3		T5	3
valid_sources[0x0c]	182526	1			T2	736		T3	17		T6	2
valid_sources[0x0d]	200990	1			T3	9		T4	5		T6	5
valid_sources[0x0e]	172286	1			T3	20		T5	1		T6	2
valid_sources[0x0f]	186953	1			T3	6		T6	3		T8	2
valid_sources[0x10]	187577	1			T3	13		T4	4		T5	3
valid_sources[0x11]	179329	1			T3	11		T5	2		T6	5
valid_sources[0x12]	195402	1			T3	29		T4	1		T5	1
valid_sources[0x13]	179425	1			T3	10		T6	2		T8	3
valid_sources[0x14]	200418	1			T3	10		T8	3		T10	110
valid_sources[0x15]	176576	1			T3	8		T6	3		T8	1
valid_sources[0x16]	195404	1			T3	12		T6	3		T8	5
valid_sources[0x17]	199968	1			T3	11		T4	7		T6	4
valid_sources[0x18]	187678	1			T3	12		T5	2		T10	121
valid_sources[0x19]	210741	1			T3	14		T6	7		T8	8
valid_sources[0x1a]	196030	1			T2	666		T3	19		T6	3
valid_sources[0x1b]	193997	1			T3	19		T5	1		T8	5
valid_sources[0x1c]	198098	1			T3	16		T4	7		T5	2
valid_sources[0x1d]	186023	1			T3	12		T8	13		T9	7
valid_sources[0x1e]	205684	1			T3	10		T6	7		T9	15
valid_sources[0x1f]	187237	1			T3	12		T8	8		T10	132
valid_sources[0x20]	305243	1			T3	6		T5	2		T6	1
valid_sources[0x21]	206599	1			T2	1938		T3	7		T4	5
valid_sources[0x22]	291154	1			T3	13		T4	4		T6	1
valid_sources[0x23]	180783	1			T3	20		T4	21		T5	1
valid_sources[0x24]	178538	1			T2	20		T3	23		T4	3
valid_sources[0x25]	191236	1			T3	8		T4	2		T8	10
valid_sources[0x26]	190203	1			T3	8		T4	24		T5	1
valid_sources[0x27]	181175	1			T3	10		T5	2		T6	2
valid_sources[0x28]	193121	1			T3	13		T6	3		T7	4888
valid_sources[0x29]	193138	1			T3	15		T4	1		T6	1
valid_sources[0x2a]	185537	1			T2	479		T3	20		T6	2
valid_sources[0x2b]	671218	1			T3	6		T6	2		T8	7
valid_sources[0x2c]	212231	1			T3	15		T5	1		T6	3
valid_sources[0x2d]	189366	1			T3	15		T5	3		T6	1
valid_sources[0x2e]	202803	1			T2	1481		T3	14		T5	1
valid_sources[0x2f]	243062	1			T3	32		T4	1		T5	1
valid_sources[0x30]	174612	1			T3	9		T5	3		T6	2
valid_sources[0x31]	174889	1			T3	15		T4	2		T5	3
valid_sources[0x32]	199798	1			T3	12		T5	2		T6	1
valid_sources[0x33]	177402	1			T3	20		T6	2		T9	2
valid_sources[0x34]	208125	1			T3	11		T6	3		T8	5
valid_sources[0x35]	175373	1			T3	24		T6	2		T8	4
valid_sources[0x36]	191832	1			T3	6		T4	2		T5	1
valid_sources[0x37]	190627	1			T3	13		T5	2		T6	1
valid_sources[0x38]	186183	1			T3	12		T5	6		T6	1
valid_sources[0x39]	185888	1			T3	19		T4	5		T5	1
valid_sources[0x3a]	199799	1			T3	12		T4	3		T8	3
valid_sources[0x3b]	185438	1			T3	16		T5	2		T6	1
valid_sources[0x3c]	201309	1			T1	6		T3	11		T6	3
valid_sources[0x3d]	181189	1			T3	22		T6	1		T8	3
valid_sources[0x3e]	175528	1			T3	13		T6	2		T8	6
valid_sources[0x3f]	186867	1			T3	17		T4	5		T5	2
valid_sources[0x40]	301981	1			T3	13		T6	1		T8	1
valid_sources[0x41]	198462	1			T3	15		T5	2		T8	4
valid_sources[0x42]	178584	1			T3	21		T6	6		T8	6
valid_sources[0x43]	180021	1			T3	12		T8	8		T9	12
valid_sources[0x44]	182008	1			T2	1132		T3	16		T5	1
valid_sources[0x45]	187854	1			T3	17		T5	2		T6	2
valid_sources[0x46]	195815	1			T3	15		T5	3		T6	6
valid_sources[0x47]	219267	1			T3	11		T6	2		T8	2
valid_sources[0x48]	184508	1			T2	26		T3	16		T4	2
valid_sources[0x49]	182945	1			T1	6		T3	7		T5	4
valid_sources[0x4a]	193888	1			T3	13		T5	4		T6	5
valid_sources[0x4b]	201230	1			T3	16		T6	8		T8	3
valid_sources[0x4c]	209756	1			T2	4349		T3	7		T5	2
valid_sources[0x4d]	180293	1			T3	13		T6	1		T8	3
valid_sources[0x4e]	174232	1			T3	9		T5	3		T6	1
valid_sources[0x4f]	199478	1			T3	15		T8	2		T10	130
valid_sources[0x50]	193070	1			T3	26		T8	1		T10	94
valid_sources[0x51]	201300	1			T3	16		T6	4		T8	8
valid_sources[0x52]	190044	1			T3	11		T5	1		T6	5
valid_sources[0x53]	268314	1			T3	10		T6	3		T8	5
valid_sources[0x54]	198350	1			T3	13		T4	2		T9	16
valid_sources[0x55]	271632	1			T3	12		T6	2		T8	9
valid_sources[0x56]	177505	1			T2	30		T3	14		T4	5
valid_sources[0x57]	171492	1			T3	28		T6	6		T8	1
valid_sources[0x58]	213654	1			T2	26		T3	17		T4	6
valid_sources[0x59]	190055	1			T3	6		T6	4		T8	3
valid_sources[0x5a]	184723	1			T3	12		T5	4		T6	1
valid_sources[0x5b]	187948	1			T3	17		T5	1		T6	4
valid_sources[0x5c]	203203	1			T3	8		T4	1		T6	4
valid_sources[0x5d]	197452	1			T3	10		T6	3		T8	3
valid_sources[0x5e]	191205	1			T3	12		T5	1		T6	6
valid_sources[0x5f]	170964	1			T3	9		T5	3		T6	1
valid_sources[0x60]	205433	1			T3	6		T6	2		T8	7
valid_sources[0x61]	203991	1			T3	14		T6	1		T9	4
valid_sources[0x62]	175961	1			T3	12		T5	1		T6	1
valid_sources[0x63]	196941	1			T3	10		T6	2		T8	1
valid_sources[0x64]	251890	1			T3	13		T9	5		T10	86
valid_sources[0x65]	216628	1			T3	14		T8	1		T10	113
valid_sources[0x66]	180733	1			T3	15		T5	2		T6	1
valid_sources[0x67]	180878	1			T3	15		T5	1		T6	5
valid_sources[0x68]	204720	1			T3	17		T5	4		T6	2
valid_sources[0x69]	182527	1			T2	578		T3	24		T6	6
valid_sources[0x6a]	252014	1			T3	24		T5	1		T6	2
valid_sources[0x6b]	330452	1			T3	18		T5	2		T6	1
valid_sources[0x6c]	299483	1			T3	19		T8	6		T10	191
valid_sources[0x6d]	241565	1			T3	19		T4	5		T5	3
valid_sources[0x6e]	220515	1			T3	25		T4	1		T6	3
valid_sources[0x6f]	182384	1			T3	20		T5	1		T6	6
valid_sources[0x70]	190706	1			T3	13		T6	5		T8	4
valid_sources[0x71]	173269	1			T3	25		T5	1		T6	1
valid_sources[0x72]	177642	1			T3	15		T5	2		T6	1
valid_sources[0x73]	193880	1			T3	16		T4	1		T5	4
valid_sources[0x74]	202309	1			T3	14		T8	1		T9	1
valid_sources[0x75]	177293	1			T3	20		T5	1		T6	2
valid_sources[0x76]	184318	1			T3	7		T5	1		T8	3
valid_sources[0x77]	195464	1			T3	21		T5	1		T6	4
valid_sources[0x78]	207847	1			T2	415		T3	13		T4	1
valid_sources[0x79]	229597	1			T3	9		T5	1		T6	1
valid_sources[0x7a]	172020	1			T3	8		T4	1		T6	6
valid_sources[0x7b]	178302	1			T3	13		T6	1		T9	2
valid_sources[0x7c]	302145	1			T3	6		T6	3		T8	8
valid_sources[0x7d]	185674	1			T3	13		T5	1		T6	1
valid_sources[0x7e]	178549	1			T2	287		T3	17		T4	1
valid_sources[0x7f]	533825	1			T3	17		T6	3		T8	4
valid_sources[0x80]	191903	1			T3	12		T6	1		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10241199

1

T1

5

T2

109

T3

1583

values[0x0]

all_enables

biggest_size

244136

1

T1

6

T2

36

T3

71

values[0x1]

all_enables

biggest_size

170472

1

T1

3

T2

16

T3

59