Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	426927876	0	0	0
ctrl_rd_A	426927876	1770	0	0
host_fifo_config_rd_A	426927876	5105	0	0
host_nack_handler_timeout_rd_A	426927876	969	0	0
host_timeout_ctrl_rd_A	426927876	739	0	0
intr_enable_rd_A	426927876	3166	0	0
ovrd_rd_A	426927876	1732	0	0
target_fifo_config_rd_A	426927876	935	0	0
target_id_rd_A	426927876	1344	0	0
target_timeout_ctrl_rd_A	426927876	893	0	0
timeout_ctrl_rd_A	426927876	1227	0	0
timing0_rd_A	426927876	971	0	0
timing1_rd_A	426927876	1038	0	0
timing2_rd_A	426927876	1052	0	0
timing3_rd_A	426927876	975	0	0
timing4_rd_A	426927876	893	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	1770	0	0
T94	1839	9	0	0
T95	13343	50	0	0
T96	6071	66	0	0
T97	2257	3	0	0
T98	2833	20	0	0
T99	2668	8	0	0
T100	8239	204	0	0
T101	28376	134	0	0
T102	12119	26	0	0
T103	1813	6	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	5105	0	0
T20	37050	0	0	0
T28	29813	0	0	0
T29	256679	0	0	0
T30	104268	0	0	0
T39	673179	0	0	0
T40	5407	0	0	0
T42	40485	0	0	0
T76	430208	214	0	0
T89	39647	0	0	0
T90	6030	0	0	0
T104	0	248	0	0
T105	0	143	0	0
T106	0	127	0	0
T107	0	123	0	0
T108	0	108	0	0
T109	0	107	0	0
T110	0	336	0	0
T111	0	216	0	0
T112	0	126	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	969	0	0
T94	1839	8	0	0
T95	13343	38	0	0
T96	6071	83	0	0
T97	2257	11	0	0
T98	2833	5	0	0
T100	8239	63	0	0
T101	28376	125	0	0
T102	12119	13	0	0
T103	1813	3	0	0
T113	1790	3	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	739	0	0
T94	1839	1	0	0
T95	13343	34	0	0
T96	6071	46	0	0
T97	2257	4	0	0
T99	2668	11	0	0
T100	8239	42	0	0
T101	28376	108	0	0
T102	12119	16	0	0
T103	1813	6	0	0
T113	1790	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	3166	0	0
T53	0	30	0	0
T61	187088	0	0	0
T106	120275	22	0	0
T107	532640	0	0	0
T114	0	29	0	0
T115	0	42	0	0
T116	0	21	0	0
T117	0	29	0	0
T118	0	19	0	0
T119	0	7	0	0
T120	0	20	0	0
T121	0	14	0	0
T122	40733	0	0	0
T123	1084	0	0	0
T124	242356	0	0	0
T125	968955	0	0	0
T126	163482	0	0	0
T127	50824	0	0	0
T128	731173	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	1732	0	0
T38	258418	0	0	0
T72	0	52	0	0
T74	1930	69	0	0
T129	0	24	0	0
T130	0	68	0	0
T131	0	30	0	0
T132	0	37	0	0
T133	0	56	0	0
T134	0	66	0	0
T135	0	53	0	0
T136	0	67	0	0
T137	128795	0	0	0
T138	292638	0	0	0
T139	255288	0	0	0
T140	16013	0	0	0
T141	42742	0	0	0
T142	350919	0	0	0
T143	17947	0	0	0
T144	487470	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	935	0	0
T95	13343	23	0	0
T96	6071	73	0	0
T97	2257	3	0	0
T98	2833	2	0	0
T99	2668	8	0	0
T100	8239	51	0	0
T101	28376	111	0	0
T102	12119	14	0	0
T103	1813	6	0	0
T113	1790	13	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	1344	0	0
T95	13343	41	0	0
T96	6071	79	0	0
T97	2257	14	0	0
T99	2668	15	0	0
T100	8239	111	0	0
T101	28376	108	0	0
T102	12119	11	0	0
T103	1813	5	0	0
T113	1790	13	0	0
T145	1702	9	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	893	0	0
T94	1839	4	0	0
T95	13343	34	0	0
T96	6071	70	0	0
T97	2257	4	0	0
T98	2833	1	0	0
T99	2668	6	0	0
T100	8239	48	0	0
T101	28376	90	0	0
T102	12119	23	0	0
T113	1790	17	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	1227	0	0
T95	13343	32	0	0
T96	6071	82	0	0
T97	2257	5	0	0
T98	2833	15	0	0
T100	8239	88	0	0
T101	28376	103	0	0
T102	12119	31	0	0
T103	1813	6	0	0
T113	1790	7	0	0
T145	1702	23	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	971	0	0
T94	1839	2	0	0
T95	13343	46	0	0
T96	6071	62	0	0
T97	2257	7	0	0
T98	2833	4	0	0
T99	2668	1	0	0
T100	8239	57	0	0
T101	28376	146	0	0
T102	12119	10	0	0
T113	1790	13	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	1038	0	0
T94	1839	9	0	0
T95	13343	100	0	0
T96	6071	57	0	0
T97	2257	4	0	0
T99	2668	10	0	0
T100	8239	68	0	0
T101	28376	140	0	0
T102	12119	26	0	0
T103	1813	10	0	0
T113	1790	12	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	1052	0	0
T94	1839	7	0	0
T95	13343	40	0	0
T96	6071	80	0	0
T97	2257	8	0	0
T98	2833	19	0	0
T100	8239	68	0	0
T101	28376	188	0	0
T102	12119	11	0	0
T103	1813	6	0	0
T146	4398	19	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	975	0	0
T94	1839	11	0	0
T95	13343	17	0	0
T96	6071	55	0	0
T97	2257	12	0	0
T98	2833	5	0	0
T99	2668	1	0	0
T100	8239	74	0	0
T101	28376	112	0	0
T102	12119	26	0	0
T113	1790	8	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426927876	893	0	0
T94	1839	9	0	0
T95	13343	33	0	0
T96	6071	72	0	0
T97	2257	2	0	0
T98	2833	13	0	0
T99	2668	12	0	0
T100	8239	48	0	0
T101	28376	143	0	0
T102	12119	6	0	0
T113	1790	9	0	0