Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

163899

1

T2

849

T7

256

T8

110

ack

14199

1

T1

26

T2

76

T7

3

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	622	1			T2	6		T7	1		T51	2
high	36695	1			T1	2		T2	188		T7	55
med	66264	1			T1	3		T2	342		T7	103
sml	73823	1			T1	21		T2	387		T7	98
all_zero	694	1			T2	2		T7	2		T8	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89067

1

T1

9

T2

439

T7

119

auto[1]

89031

1

T1

17

T2

486

T7

140

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122417

1

T1

17

T2

635

T7

162

auto[1]

55681

1

T1

9

T2

290

T7

97

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170729

1

T1

9

T2

889

T7

258

auto[1]

7369

1

T1

17

T2

36

T7

1

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168193

1

T1

17

T2

878

T7

257

auto[1]

9905

1

T1

9

T2

47

T7

2

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169129

1

T1

18

T2

886

T7

258

auto[1]

8969

1

T1

8

T2

39

T7

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89067

1

T1

9

T2

439

T7

119

auto[1]

89031

1

T1

17

T2

486

T7

140

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122417

1

T1

17

T2

635

T7

162

auto[1]

55681

1

T1

9

T2

290

T7

97

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170729

1

T1

9

T2

889

T7

258

auto[1]

7369

1

T1

17

T2

36

T7

1

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168193

1

T1

17

T2

878

T7

257

auto[1]

9905

1

T1

9

T2

47

T7

2

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169129

1

T1

18

T2

886

T7

258

auto[1]

8969

1

T1

8

T2

39

T7

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

3

1

T92

1

T93

1

T248

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T103

1

T249

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T140

1

T145

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

262

1

T28

5

T44

2

T87

6

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

156

1

T2

1

T28

2

T87

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

149

1

T2

1

T51

1

T52

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

584

1

T2

3

T51

1

T43

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

266

1

T8

1

T51

1

T43

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

274

1

T51

2

T43

2

T52

3

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

564

1

T2

1

T51

2

T43

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

291

1

T2

1

T51

2

T43

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

270

1

T2

1

T51

1

T43

2

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T43

1

T36

1

T250

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T251

1

T40

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T252

1

T34

1

T253

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	52536	1			T2	268		T7	78		T8	31
write_address_byte	9905	1			T1	9		T2	47		T7	2
read_with_ack	2024	1			T1	9		T2	4		T8	1
read_with_nack	5345	1			T1	8		T2	32		T7	1
stop_byte	8969	1			T1	8		T2	39		T7	1
write_address_byte_nak	5058	1			T2	10		T8	8		T51	18
data_byte_nack	163899	1			T2	849		T7	256		T8	110
stop_byte_nack	5512	1			T2	11		T8	9		T51	17
nakok_byte_nack	81867	1			T2	441		T7	138		T8	53
nakok_addr_byte_nack	2535	1			T2	6		T8	3		T51	12