Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	413317120	0	0	0
ctrl_rd_A	413317120	1115	0	0
host_fifo_config_rd_A	413317120	4622	0	0
host_nack_handler_timeout_rd_A	413317120	1090	0	0
host_timeout_ctrl_rd_A	413317120	898	0	0
intr_enable_rd_A	413317120	1974	0	0
ovrd_rd_A	413317120	1820	0	0
target_fifo_config_rd_A	413317120	969	0	0
target_id_rd_A	413317120	942	0	0
target_timeout_ctrl_rd_A	413317120	876	0	0
timeout_ctrl_rd_A	413317120	1061	0	0
timing0_rd_A	413317120	970	0	0
timing1_rd_A	413317120	1026	0	0
timing2_rd_A	413317120	933	0	0
timing3_rd_A	413317120	958	0	0
timing4_rd_A	413317120	1045	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	1115	0	0
T77	1236	33	0	0
T78	2358	24	0	0
T79	7667	130	0	0
T80	1910	21	0	0
T81	7507	28	0	0
T82	12337	19	0	0
T83	2341	11	0	0
T84	2233	19	0	0
T85	8525	1	0	0
T86	2557	29	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	4622	0	0
T26	178267	0	0	0
T29	970022	0	0	0
T46	10178	0	0	0
T60	2192	0	0	0
T87	139226	542	0	0
T88	0	201	0	0
T89	0	142	0	0
T90	0	108	0	0
T91	0	402	0	0
T92	0	318	0	0
T93	0	596	0	0
T94	0	121	0	0
T95	0	218	0	0
T96	0	139	0	0
T97	68168	0	0	0
T98	130347	0	0	0
T99	139007	0	0	0
T100	107230	0	0	0
T101	19131	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	1090	0	0
T78	2358	18	0	0
T79	7667	134	0	0
T80	1910	11	0	0
T81	7507	27	0	0
T82	12337	21	0	0
T83	2341	27	0	0
T84	2233	5	0	0
T85	8525	8	0	0
T86	2557	17	0	0
T102	7058	8	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	898	0	0
T77	1236	2	0	0
T78	2358	12	0	0
T79	7667	107	0	0
T80	1910	9	0	0
T81	7507	45	0	0
T82	12337	15	0	0
T83	2341	18	0	0
T84	2233	9	0	0
T85	8525	19	0	0
T86	2557	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	1974	0	0
T26	178267	0	0	0
T29	970022	0	0	0
T46	10178	0	0	0
T60	2192	0	0	0
T77	0	4	0	0
T78	0	61	0	0
T87	139226	7	0	0
T94	0	11	0	0
T97	68168	0	0	0
T98	130347	0	0	0
T99	139007	0	0	0
T100	107230	0	0	0
T101	19131	0	0	0
T103	0	29	0	0
T104	0	9	0	0
T105	0	12	0	0
T106	0	18	0	0
T107	0	18	0	0
T108	0	11	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	1820	0	0
T28	140253	0	0	0
T44	281449	0	0	0
T57	115758	0	0	0
T59	2131	56	0	0
T60	0	75	0	0
T109	0	45	0	0
T110	0	25	0	0
T111	0	82	0	0
T112	0	58	0	0
T113	0	44	0	0
T114	0	55	0	0
T115	0	36	0	0
T116	0	66	0	0
T117	946205	0	0	0
T118	304289	0	0	0
T119	100518	0	0	0
T120	167325	0	0	0
T121	29146	0	0	0
T122	128814	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	969	0	0
T77	1236	2	0	0
T78	2358	18	0	0
T79	7667	123	0	0
T80	1910	1	0	0
T81	7507	47	0	0
T82	12337	24	0	0
T83	2341	22	0	0
T84	2233	4	0	0
T85	8525	3	0	0
T86	2557	9	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	942	0	0
T77	1236	1	0	0
T78	2358	5	0	0
T79	7667	122	0	0
T80	1910	2	0	0
T81	7507	33	0	0
T82	12337	17	0	0
T83	2341	9	0	0
T84	2233	7	0	0
T85	8525	3	0	0
T86	2557	21	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	876	0	0
T78	2358	6	0	0
T79	7667	92	0	0
T80	1910	15	0	0
T81	7507	48	0	0
T82	12337	4	0	0
T83	2341	21	0	0
T84	2233	6	0	0
T85	8525	8	0	0
T86	2557	4	0	0
T102	7058	14	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	1061	0	0
T78	2358	28	0	0
T79	7667	123	0	0
T80	1910	9	0	0
T81	7507	29	0	0
T82	12337	32	0	0
T83	2341	14	0	0
T84	2233	2	0	0
T85	8525	11	0	0
T86	2557	11	0	0
T102	7058	16	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	970	0	0
T77	1236	9	0	0
T78	2358	17	0	0
T79	7667	111	0	0
T80	1910	4	0	0
T81	7507	48	0	0
T82	12337	22	0	0
T83	2341	14	0	0
T84	2233	4	0	0
T85	8525	22	0	0
T86	2557	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	1026	0	0
T77	1236	5	0	0
T78	2358	5	0	0
T79	7667	126	0	0
T80	1910	12	0	0
T81	7507	68	0	0
T82	12337	30	0	0
T83	2341	10	0	0
T84	2233	11	0	0
T85	8525	1	0	0
T86	2557	4	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	933	0	0
T78	2358	3	0	0
T79	7667	115	0	0
T80	1910	8	0	0
T81	7507	35	0	0
T82	12337	10	0	0
T83	2341	11	0	0
T84	2233	11	0	0
T85	8525	3	0	0
T86	2557	7	0	0
T102	7058	26	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	958	0	0
T78	2358	6	0	0
T79	7667	116	0	0
T80	1910	4	0	0
T81	7507	45	0	0
T82	12337	18	0	0
T83	2341	18	0	0
T84	2233	11	0	0
T85	8525	38	0	0
T86	2557	18	0	0
T102	7058	21	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413317120	1045	0	0
T77	1236	3	0	0
T78	2358	12	0	0
T79	7667	126	0	0
T80	1910	3	0	0
T81	7507	66	0	0
T82	12337	36	0	0
T83	2341	16	0	0
T84	2233	14	0	0
T85	8525	10	0	0
T86	2557	14	0	0