Unified Coverage Report :: Group :: i2c_env_pkg::i2c_scl_sda_override_cg

Group : i2c_env_pkg::i2c_scl_sda_override_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
0.00	0.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.scl_sda_override_cg	0.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.scl_sda_override_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.scl_sda_override_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00
Crosses	8	8	0	0.00

Variables for Group Instance i2c_env_pkg.scl_sda_override_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_sclval	2	2	0	0.00	100	1	1	2
cp_sdaval	2	2	0	0.00	100	1	1	2
cp_txorvden	2	2	0	0.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.scl_sda_override_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_txorvden_x_sclval	4	4	0	0.00	100	1	1	0
cp_txorvden_x_sdaval	4	4	0	0.00	100	1	1	0

Summary for Variable cp_sclval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_sclval

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_sdaval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_sdaval

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_txorvden

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_txorvden

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross cp_txorvden_x_sclval

Samples crossed: cp_txorvden cp_sclval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for cp_txorvden_x_sclval

Uncovered bins

cp_txorvden	cp_sclval	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross cp_txorvden_x_sdaval

Samples crossed: cp_txorvden cp_sdaval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for cp_txorvden_x_sdaval

Uncovered bins

cp_txorvden	cp_sdaval	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4