Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

44360

1

T1

583

T2

290

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39187	1			T1	166		T2	493		T3	11
values[0x0]	16933	1			T1	201		T2	160		T3	7
values[0x1]	17794	1			T1	286		T2	141		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

53066

1

T1

632

T2

474

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	304	1			T3	2		T6	2		T5	1
valid_sources[0x01]	161	1			T4	1		T6	4		T12	2
valid_sources[0x02]	240	1			T1	1		T2	24		T4	4
valid_sources[0x03]	558	1			T2	1		T4	4		T6	2
valid_sources[0x04]	464	1			T3	1		T4	3		T6	3
valid_sources[0x05]	235	1			T4	1		T6	7		T12	6
valid_sources[0x06]	406	1			T1	18		T2	12		T4	2
valid_sources[0x07]	216	1			T4	3		T6	3		T5	3
valid_sources[0x08]	517	1			T4	3		T6	3		T5	2
valid_sources[0x09]	210	1			T4	3		T6	2		T5	1
valid_sources[0x0a]	239	1			T4	6		T6	5		T5	1
valid_sources[0x0b]	280	1			T4	1		T6	3		T5	1
valid_sources[0x0c]	166	1			T2	4		T4	1		T6	1
valid_sources[0x0d]	326	1			T4	2		T6	3		T5	2
valid_sources[0x0e]	194	1			T4	3		T6	2		T12	5
valid_sources[0x0f]	160	1			T4	5		T6	2		T12	1
valid_sources[0x10]	229	1			T4	2		T6	5		T5	2
valid_sources[0x11]	283	1			T4	3		T6	2		T5	1
valid_sources[0x12]	428	1			T4	3		T6	10		T5	4
valid_sources[0x13]	220	1			T6	4		T5	2		T11	1
valid_sources[0x14]	208	1			T4	1		T6	2		T11	4
valid_sources[0x15]	483	1			T4	1		T6	2		T12	5
valid_sources[0x16]	237	1			T4	1		T6	4		T5	1
valid_sources[0x17]	168	1			T4	2		T6	7		T8	2
valid_sources[0x18]	158	1			T2	1		T3	1		T4	1
valid_sources[0x19]	317	1			T4	2		T6	8		T9	1
valid_sources[0x1a]	267	1			T2	1		T4	2		T6	4
valid_sources[0x1b]	307	1			T2	6		T4	1		T6	4
valid_sources[0x1c]	303	1			T4	1		T5	2		T9	1
valid_sources[0x1d]	534	1			T1	7		T4	5		T6	4
valid_sources[0x1e]	194	1			T4	3		T6	5		T5	2
valid_sources[0x1f]	314	1			T4	1		T6	3		T5	6
valid_sources[0x20]	267	1			T4	3		T6	4		T5	2
valid_sources[0x21]	394	1			T1	68		T2	15		T3	1
valid_sources[0x22]	219	1			T4	2		T6	6		T5	1
valid_sources[0x23]	240	1			T4	1		T6	7		T12	5
valid_sources[0x24]	239	1			T4	2		T6	1		T5	1
valid_sources[0x25]	209	1			T1	8		T6	3		T10	3
valid_sources[0x26]	436	1			T6	2		T5	2		T8	1
valid_sources[0x27]	604	1			T2	4		T6	2		T5	2
valid_sources[0x28]	324	1			T2	31		T3	1		T4	3
valid_sources[0x29]	216	1			T4	3		T6	4		T12	5
valid_sources[0x2a]	361	1			T2	13		T4	1		T6	2
valid_sources[0x2b]	392	1			T3	1		T4	1		T6	4
valid_sources[0x2c]	223	1			T2	15		T4	4		T6	2
valid_sources[0x2d]	227	1			T2	2		T4	6		T6	2
valid_sources[0x2e]	214	1			T4	2		T6	3		T5	2
valid_sources[0x2f]	211	1			T4	6		T6	5		T5	2
valid_sources[0x30]	211	1			T4	2		T6	4		T13	8
valid_sources[0x31]	320	1			T3	1		T4	2		T6	1
valid_sources[0x32]	410	1			T6	2		T17	2		T12	3
valid_sources[0x33]	241	1			T4	4		T6	4		T5	1
valid_sources[0x34]	287	1			T3	1		T4	1		T6	4
valid_sources[0x35]	416	1			T4	2		T6	6		T5	1
valid_sources[0x36]	249	1			T4	4		T6	3		T5	3
valid_sources[0x37]	208	1			T4	4		T6	3		T5	2
valid_sources[0x38]	342	1			T1	1		T4	3		T6	3
valid_sources[0x39]	344	1			T4	2		T6	1		T18	4
valid_sources[0x3a]	243	1			T3	1		T4	3		T6	2
valid_sources[0x3b]	378	1			T4	1		T6	4		T5	2
valid_sources[0x3c]	245	1			T4	1		T6	2		T5	2
valid_sources[0x3d]	240	1			T4	5		T6	2		T5	2
valid_sources[0x3e]	280	1			T2	1		T4	2		T6	3
valid_sources[0x3f]	227	1			T4	5		T6	2		T5	1
valid_sources[0x40]	393	1			T2	2		T4	1		T6	5
valid_sources[0x41]	346	1			T2	7		T4	2		T6	2
valid_sources[0x42]	255	1			T4	1		T6	3		T5	2
valid_sources[0x43]	189	1			T2	20		T4	1		T6	3
valid_sources[0x44]	181	1			T1	10		T4	1		T6	2
valid_sources[0x45]	195	1			T6	3		T11	10		T12	2
valid_sources[0x46]	199	1			T4	3		T6	4		T5	2
valid_sources[0x47]	271	1			T4	2		T6	3		T10	7
valid_sources[0x48]	298	1			T4	5		T6	7		T5	2
valid_sources[0x49]	240	1			T4	4		T6	2		T5	1
valid_sources[0x4a]	145	1			T4	3		T6	1		T5	2
valid_sources[0x4b]	224	1			T6	2		T11	6		T12	1
valid_sources[0x4c]	419	1			T4	1		T6	2		T5	1
valid_sources[0x4d]	403	1			T6	3		T5	3		T11	1
valid_sources[0x4e]	172	1			T1	1		T6	3		T10	2
valid_sources[0x4f]	190	1			T4	5		T6	2		T5	2
valid_sources[0x50]	212	1			T4	1		T6	4		T5	1
valid_sources[0x51]	238	1			T4	1		T6	2		T5	2
valid_sources[0x52]	230	1			T4	1		T5	4		T10	53
valid_sources[0x53]	447	1			T2	19		T4	5		T6	5
valid_sources[0x54]	330	1			T2	11		T4	4		T6	3
valid_sources[0x55]	267	1			T4	4		T6	3		T5	1
valid_sources[0x56]	336	1			T4	4		T6	6		T5	2
valid_sources[0x57]	258	1			T4	2		T6	3		T5	2
valid_sources[0x58]	181	1			T2	13		T4	5		T6	2
valid_sources[0x59]	291	1			T2	2		T4	3		T6	1
valid_sources[0x5a]	227	1			T2	28		T4	3		T12	1
valid_sources[0x5b]	207	1			T4	3		T6	7		T5	1
valid_sources[0x5c]	234	1			T6	2		T5	1		T12	4
valid_sources[0x5d]	306	1			T4	3		T6	1		T5	4
valid_sources[0x5e]	329	1			T4	3		T6	9		T5	1
valid_sources[0x5f]	281	1			T4	3		T6	1		T5	3
valid_sources[0x60]	231	1			T4	2		T6	3		T5	1
valid_sources[0x61]	320	1			T2	23		T6	2		T5	1
valid_sources[0x62]	200	1			T1	13		T6	4		T17	1
valid_sources[0x63]	237	1			T2	4		T4	1		T6	3
valid_sources[0x64]	197	1			T4	3		T6	3		T12	3
valid_sources[0x65]	213	1			T4	2		T6	4		T5	1
valid_sources[0x66]	319	1			T6	3		T5	1		T12	1
valid_sources[0x67]	230	1			T2	11		T4	2		T6	1
valid_sources[0x68]	340	1			T4	4		T6	3		T5	1
valid_sources[0x69]	232	1			T4	1		T6	3		T5	1
valid_sources[0x6a]	282	1			T2	16		T4	1		T6	5
valid_sources[0x6b]	336	1			T4	1		T6	5		T11	1
valid_sources[0x6c]	249	1			T4	5		T6	1		T5	2
valid_sources[0x6d]	357	1			T1	22		T2	20		T4	1
valid_sources[0x6e]	319	1			T2	27		T4	3		T6	3
valid_sources[0x6f]	411	1			T4	2		T5	1		T10	10
valid_sources[0x70]	322	1			T4	5		T6	3		T5	2
valid_sources[0x71]	431	1			T2	27		T4	4		T6	2
valid_sources[0x72]	439	1			T2	18		T6	6		T5	2
valid_sources[0x73]	159	1			T4	3		T6	4		T12	2
valid_sources[0x74]	270	1			T2	7		T4	1		T6	6
valid_sources[0x75]	171	1			T4	5		T6	4		T5	1
valid_sources[0x76]	238	1			T4	4		T6	3		T12	5
valid_sources[0x77]	172	1			T4	1		T6	6		T12	1
valid_sources[0x78]	179	1			T4	3		T6	3		T5	1
valid_sources[0x79]	195	1			T6	4		T5	2		T9	1
valid_sources[0x7a]	507	1			T4	1		T6	3		T5	1
valid_sources[0x7b]	374	1			T6	3		T5	1		T12	2
valid_sources[0x7c]	310	1			T2	8		T4	2		T6	5
valid_sources[0x7d]	193	1			T4	4		T6	2		T5	2
valid_sources[0x7e]	230	1			T4	4		T6	7		T12	3
valid_sources[0x7f]	312	1			T4	1		T6	1		T5	1
valid_sources[0x80]	259	1			T2	3		T4	1		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17167

1

T1

166

T2

72

T3

5

values[0x0]

all_enables

biggest_size

14076

1

T1

197

T2

130

T3

3

values[0x1]

all_enables

biggest_size

13117

1

T1

220

T2

88

T3

3