Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.62	0.00	0.00	94.87				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	732437	0	0	0
ctrl_rd_A	732437	2700	0	0
host_fifo_config_rd_A	732437	1748	0	0
host_nack_handler_timeout_rd_A	732437	1606	0	0
host_timeout_ctrl_rd_A	732437	1308	0	0
intr_enable_rd_A	732437	5840	0	0
ovrd_rd_A	732437	2015	0	0
target_fifo_config_rd_A	732437	1532	0	0
target_id_rd_A	732437	2440	0	0
target_timeout_ctrl_rd_A	732437	1825	0	0
timeout_ctrl_rd_A	732437	2135	0	0
timing0_rd_A	732437	1613	0	0
timing1_rd_A	732437	1752	0	0
timing2_rd_A	732437	1590	0	0
timing3_rd_A	732437	1654	0	0
timing4_rd_A	732437	1778	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	2700	0	0
T4	5675	26	0	0
T5	2875	0	0	0
T6	15213	38	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	29	0	0
T12	9847	14	0	0
T13	0	20	0	0
T15	0	22	0	0
T17	1296	0	0	0
T19	0	197	0	0
T20	0	16	0	0
T21	0	19	0	0
T56	0	15	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1748	0	0
T4	5675	2	0	0
T5	2875	0	0	0
T6	15213	30	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	15	0	0
T12	9847	38	0	0
T13	0	20	0	0
T15	0	24	0	0
T17	1296	0	0	0
T19	0	132	0	0
T20	0	13	0	0
T21	0	1	0	0
T56	0	25	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1606	0	0
T4	5675	21	0	0
T5	2875	0	0	0
T6	15213	43	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	13	0	0
T12	9847	7	0	0
T13	0	7	0	0
T15	0	14	0	0
T17	1296	0	0	0
T19	0	92	0	0
T20	0	21	0	0
T21	0	7	0	0
T56	0	24	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1308	0	0
T4	5675	31	0	0
T5	2875	0	0	0
T6	15213	35	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	7	0	0
T12	9847	29	0	0
T13	0	30	0	0
T15	0	4	0	0
T17	1296	0	0	0
T19	0	65	0	0
T20	0	3	0	0
T56	0	8	0	0
T57	0	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	5840	0	0
T4	5675	3	0	0
T5	2875	0	0	0
T6	15213	28	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	5	0	0
T12	9847	47	0	0
T13	0	46	0	0
T15	0	10	0	0
T17	1296	0	0	0
T19	0	543	0	0
T20	0	15	0	0
T54	0	9	0	0
T58	0	10	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	2015	0	0
T4	5675	47	0	0
T5	2875	0	0	0
T6	15213	35	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	23	0	0
T12	9847	26	0	0
T13	0	13	0	0
T15	0	12	0	0
T17	1296	0	0	0
T19	0	193	0	0
T20	0	10	0	0
T21	0	9	0	0
T56	0	11	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1532	0	0
T4	5675	37	0	0
T5	2875	0	0	0
T6	15213	14	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	3	0	0
T12	9847	21	0	0
T13	0	37	0	0
T15	0	25	0	0
T17	1296	0	0	0
T19	0	126	0	0
T20	0	18	0	0
T21	0	3	0	0
T56	0	1	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	2440	0	0
T4	5675	2	0	0
T5	2875	0	0	0
T6	15213	20	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	6	0	0
T12	9847	12	0	0
T13	0	24	0	0
T15	0	35	0	0
T17	1296	0	0	0
T19	0	216	0	0
T20	0	8	0	0
T21	0	11	0	0
T56	0	25	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1825	0	0
T4	5675	35	0	0
T5	2875	0	0	0
T6	15213	66	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	6	0	0
T12	9847	34	0	0
T13	0	18	0	0
T15	0	16	0	0
T17	1296	0	0	0
T19	0	110	0	0
T20	0	3	0	0
T21	0	3	0	0
T56	0	16	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	2135	0	0
T4	5675	18	0	0
T5	2875	0	0	0
T6	15213	46	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	26	0	0
T12	9847	20	0	0
T13	0	21	0	0
T15	0	29	0	0
T17	1296	0	0	0
T19	0	184	0	0
T22	0	69	0	0
T56	0	11	0	0
T57	0	88	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1613	0	0
T4	5675	9	0	0
T5	2875	0	0	0
T6	15213	14	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	11	0	0
T12	9847	17	0	0
T13	0	9	0	0
T15	0	26	0	0
T17	1296	0	0	0
T19	0	122	0	0
T20	0	6	0	0
T56	0	4	0	0
T57	0	75	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1752	0	0
T4	5675	49	0	0
T5	2875	0	0	0
T6	15213	22	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	9	0	0
T12	9847	37	0	0
T13	0	18	0	0
T15	0	28	0	0
T17	1296	0	0	0
T19	0	142	0	0
T20	0	9	0	0
T21	0	2	0	0
T56	0	16	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1590	0	0
T4	5675	8	0	0
T5	2875	0	0	0
T6	15213	45	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	23	0	0
T12	9847	27	0	0
T13	0	34	0	0
T15	0	11	0	0
T17	1296	0	0	0
T19	0	99	0	0
T22	0	40	0	0
T34	0	147	0	0
T57	0	58	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1654	0	0
T4	5675	8	0	0
T5	2875	0	0	0
T6	15213	20	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	12	0	0
T12	9847	11	0	0
T13	0	34	0	0
T15	0	26	0	0
T17	1296	0	0	0
T19	0	119	0	0
T20	0	19	0	0
T21	0	3	0	0
T57	0	48	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732437	1778	0	0
T4	5675	16	0	0
T5	2875	0	0	0
T6	15213	35	0	0
T7	1574	0	0	0
T8	1052	0	0	0
T9	1580	0	0	0
T10	2625	0	0	0
T11	3090	14	0	0
T12	9847	32	0	0
T13	0	5	0	0
T15	0	13	0	0
T17	1296	0	0	0
T19	0	120	0	0
T20	0	16	0	0
T21	0	6	0	0
T56	0	12	0	0