Line Coverage for Module :
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Line Coverage for Module :
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Module :
i2c_fifo_sync_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 44 | 86.27 |
Logical | 51 | 44 | 86.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T64,T35 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T41,T78,T79 |
1 | 1 | Covered | T1,T2,T4 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T81,T41,T115 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T81,T41,T115 |
1 | Covered | T1,T2,T4 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T81,T41,T115 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T9 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T9 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T141 |
1 | 1 | Covered | T4,T6,T9 |
Branch Coverage for Module :
i2c_fifo_sync_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T2,T4 |
1 |
0 |
- |
Covered |
T1,T2,T4 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
i2c_fifo_sync_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5764 |
5764 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T7 |
4 |
4 |
0 |
0 |
T8 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T10 |
4 |
4 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5764 |
5764 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T7 |
4 |
4 |
0 |
0 |
T8 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T10 |
4 |
4 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1622159032 |
1621441452 |
0 |
0 |
T1 |
125040 |
124800 |
0 |
0 |
T2 |
383128 |
382764 |
0 |
0 |
T3 |
225624 |
225420 |
0 |
0 |
T4 |
1523768 |
1523388 |
0 |
0 |
T5 |
279336 |
279060 |
0 |
0 |
T6 |
297940 |
297716 |
0 |
0 |
T7 |
7412 |
7076 |
0 |
0 |
T8 |
495708 |
495676 |
0 |
0 |
T9 |
457916 |
457684 |
0 |
0 |
T10 |
221488 |
221244 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1622159032 |
1283596860 |
0 |
0 |
T1 |
125040 |
96857 |
0 |
0 |
T2 |
383128 |
306793 |
0 |
0 |
T3 |
225624 |
171460 |
0 |
0 |
T4 |
1523768 |
1216509 |
0 |
0 |
T5 |
279336 |
225502 |
0 |
0 |
T6 |
297940 |
229299 |
0 |
0 |
T7 |
7412 |
7076 |
0 |
0 |
T8 |
495708 |
449125 |
0 |
0 |
T9 |
457916 |
1755570 |
0 |
0 |
T10 |
221488 |
197796 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1622159032 |
18847987 |
0 |
0 |
T4 |
380942 |
229051 |
0 |
0 |
T5 |
69834 |
0 |
0 |
0 |
T6 |
74485 |
42410 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
0 |
0 |
0 |
T9 |
228958 |
131401 |
0 |
0 |
T10 |
110744 |
0 |
0 |
0 |
T15 |
187321 |
27 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
T18 |
249560 |
0 |
0 |
0 |
T20 |
105260 |
0 |
0 |
0 |
T33 |
0 |
277 |
0 |
0 |
T34 |
0 |
10556 |
0 |
0 |
T35 |
0 |
25704 |
0 |
0 |
T40 |
0 |
3028 |
0 |
0 |
T41 |
0 |
45688 |
0 |
0 |
T42 |
0 |
75585 |
0 |
0 |
T43 |
501940 |
16981 |
0 |
0 |
T44 |
53395 |
0 |
0 |
0 |
T49 |
0 |
108211 |
0 |
0 |
T64 |
0 |
2533 |
0 |
0 |
T74 |
210794 |
0 |
0 |
0 |
T88 |
0 |
10 |
0 |
0 |
T91 |
0 |
9643 |
0 |
0 |
T92 |
0 |
2736 |
0 |
0 |
T96 |
0 |
4 |
0 |
0 |
T134 |
0 |
3260 |
0 |
0 |
T142 |
0 |
35676 |
0 |
0 |
T143 |
0 |
500622 |
0 |
0 |
T144 |
128010 |
0 |
0 |
0 |
T145 |
192677 |
0 |
0 |
0 |
T146 |
84495 |
0 |
0 |
0 |
T147 |
59077 |
0 |
0 |
0 |
T148 |
129924 |
0 |
0 |
0 |
T149 |
992331 |
0 |
0 |
0 |
T150 |
108801 |
0 |
0 |
0 |
T151 |
16336 |
0 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1622159032 |
675756 |
0 |
0 |
T1 |
31260 |
0 |
0 |
0 |
T2 |
191564 |
334 |
0 |
0 |
T3 |
112812 |
288 |
0 |
0 |
T4 |
1142826 |
261 |
0 |
0 |
T5 |
209502 |
231 |
0 |
0 |
T6 |
223455 |
0 |
0 |
0 |
T7 |
5559 |
0 |
0 |
0 |
T8 |
371781 |
5 |
0 |
0 |
T9 |
457916 |
3393 |
0 |
0 |
T10 |
221488 |
113 |
0 |
0 |
T11 |
26729 |
82 |
0 |
0 |
T12 |
0 |
142 |
0 |
0 |
T17 |
0 |
890 |
0 |
0 |
T18 |
249560 |
733 |
0 |
0 |
T19 |
0 |
744 |
0 |
0 |
T20 |
157890 |
0 |
0 |
0 |
T25 |
0 |
193 |
0 |
0 |
T32 |
62584 |
0 |
0 |
0 |
T34 |
0 |
547 |
0 |
0 |
T35 |
0 |
32 |
0 |
0 |
T38 |
635197 |
15 |
0 |
0 |
T43 |
501940 |
726 |
0 |
0 |
T44 |
53395 |
107 |
0 |
0 |
T51 |
0 |
52 |
0 |
0 |
T63 |
60621 |
115 |
0 |
0 |
T64 |
0 |
744 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1622159032 |
675756 |
0 |
0 |
T1 |
31260 |
0 |
0 |
0 |
T2 |
191564 |
334 |
0 |
0 |
T3 |
112812 |
288 |
0 |
0 |
T4 |
1142826 |
261 |
0 |
0 |
T5 |
209502 |
231 |
0 |
0 |
T6 |
223455 |
0 |
0 |
0 |
T7 |
5559 |
0 |
0 |
0 |
T8 |
371781 |
5 |
0 |
0 |
T9 |
457916 |
3393 |
0 |
0 |
T10 |
221488 |
113 |
0 |
0 |
T11 |
26729 |
82 |
0 |
0 |
T12 |
0 |
142 |
0 |
0 |
T17 |
0 |
890 |
0 |
0 |
T18 |
249560 |
733 |
0 |
0 |
T19 |
0 |
744 |
0 |
0 |
T20 |
157890 |
0 |
0 |
0 |
T25 |
0 |
193 |
0 |
0 |
T32 |
62584 |
0 |
0 |
0 |
T34 |
0 |
547 |
0 |
0 |
T35 |
0 |
32 |
0 |
0 |
T38 |
635197 |
15 |
0 |
0 |
T43 |
501940 |
726 |
0 |
0 |
T44 |
53395 |
107 |
0 |
0 |
T51 |
0 |
52 |
0 |
0 |
T63 |
60621 |
115 |
0 |
0 |
T64 |
0 |
744 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 39 | 76.47 |
Logical | 51 | 39 | 76.47 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T78,T79,T80 |
1 | 1 | Covered | T1,T2,T5 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T5 |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Not Covered | |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T5 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T5 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T5 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T5 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T33,T34 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T33,T34 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T6,T33,T34 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T2,T5 |
1 |
0 |
- |
Covered |
T1,T2,T5 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1441 |
1441 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1441 |
1441 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
405360363 |
0 |
0 |
T1 |
31260 |
31200 |
0 |
0 |
T2 |
95782 |
95691 |
0 |
0 |
T3 |
56406 |
56355 |
0 |
0 |
T4 |
380942 |
380847 |
0 |
0 |
T5 |
69834 |
69765 |
0 |
0 |
T6 |
74485 |
74429 |
0 |
0 |
T7 |
1853 |
1769 |
0 |
0 |
T8 |
123927 |
123919 |
0 |
0 |
T9 |
114479 |
114421 |
0 |
0 |
T10 |
55372 |
55311 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
335604073 |
0 |
0 |
T1 |
31260 |
3257 |
0 |
0 |
T2 |
95782 |
66910 |
0 |
0 |
T3 |
56406 |
56355 |
0 |
0 |
T4 |
380942 |
380847 |
0 |
0 |
T5 |
69834 |
47989 |
0 |
0 |
T6 |
74485 |
6012 |
0 |
0 |
T7 |
1853 |
1769 |
0 |
0 |
T8 |
123927 |
123919 |
0 |
0 |
T9 |
114479 |
114421 |
0 |
0 |
T10 |
55372 |
55311 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
4977944 |
0 |
0 |
T6 |
74485 |
42410 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
0 |
0 |
0 |
T9 |
114479 |
0 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T18 |
124780 |
0 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T32 |
62584 |
0 |
0 |
0 |
T33 |
0 |
277 |
0 |
0 |
T34 |
0 |
10556 |
0 |
0 |
T43 |
250970 |
0 |
0 |
0 |
T44 |
53395 |
0 |
0 |
0 |
T81 |
0 |
59805 |
0 |
0 |
T82 |
0 |
46599 |
0 |
0 |
T90 |
0 |
313 |
0 |
0 |
T93 |
0 |
83187 |
0 |
0 |
T114 |
0 |
49989 |
0 |
0 |
T115 |
0 |
9081 |
0 |
0 |
T152 |
0 |
71834 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
167764 |
0 |
0 |
T1 |
31260 |
138 |
0 |
0 |
T2 |
95782 |
196 |
0 |
0 |
T3 |
56406 |
0 |
0 |
0 |
T4 |
380942 |
0 |
0 |
0 |
T5 |
69834 |
150 |
0 |
0 |
T6 |
74485 |
203 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
0 |
0 |
0 |
T9 |
114479 |
0 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T11 |
0 |
66 |
0 |
0 |
T20 |
0 |
260 |
0 |
0 |
T25 |
0 |
18 |
0 |
0 |
T32 |
0 |
283 |
0 |
0 |
T33 |
0 |
115 |
0 |
0 |
T34 |
0 |
1057 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
167764 |
0 |
0 |
T1 |
31260 |
138 |
0 |
0 |
T2 |
95782 |
196 |
0 |
0 |
T3 |
56406 |
0 |
0 |
0 |
T4 |
380942 |
0 |
0 |
0 |
T5 |
69834 |
150 |
0 |
0 |
T6 |
74485 |
203 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
0 |
0 |
0 |
T9 |
114479 |
0 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T11 |
0 |
66 |
0 |
0 |
T20 |
0 |
260 |
0 |
0 |
T25 |
0 |
18 |
0 |
0 |
T32 |
0 |
283 |
0 |
0 |
T33 |
0 |
115 |
0 |
0 |
T34 |
0 |
1057 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T8,T9 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T41,T74,T75 |
1 | 1 | Covered | T4,T8,T9 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T8,T9 |
1 | 1 | Covered | T4,T8,T9 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T8,T9 |
1 | 1 | Covered | T4,T8,T9 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T8,T9 |
0 | 1 | Covered | T4,T8,T9 |
1 | 0 | Covered | T41,T74,T75 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T41,T74,T75 |
1 | Covered | T4,T8,T9 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T41,T74,T75 |
0 | 1 | Covered | T4,T8,T9 |
1 | 0 | Covered | T4,T8,T9 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T8,T9 |
1 | 1 | Covered | T4,T8,T9 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T8,T9 |
1 | 1 | Covered | T4,T8,T9 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T8,T9 |
1 | 1 | Covered | T4,T8,T9 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T8,T9 |
1 | 1 | Covered | T4,T8,T9 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T8,T9 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T8,T9 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T8,T9 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T9,T43 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T9,T43 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T8,T9 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T9,T43 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T8,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T4,T8,T9 |
1 |
0 |
- |
Covered |
T4,T8,T9 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1441 |
1441 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1441 |
1441 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
405360363 |
0 |
0 |
T1 |
31260 |
31200 |
0 |
0 |
T2 |
95782 |
95691 |
0 |
0 |
T3 |
56406 |
56355 |
0 |
0 |
T4 |
380942 |
380847 |
0 |
0 |
T5 |
69834 |
69765 |
0 |
0 |
T6 |
74485 |
74429 |
0 |
0 |
T7 |
1853 |
1769 |
0 |
0 |
T8 |
123927 |
123919 |
0 |
0 |
T9 |
114479 |
114421 |
0 |
0 |
T10 |
55372 |
55311 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
347264079 |
0 |
0 |
T1 |
31260 |
31200 |
0 |
0 |
T2 |
95782 |
95691 |
0 |
0 |
T3 |
56406 |
56355 |
0 |
0 |
T4 |
380942 |
73968 |
0 |
0 |
T5 |
69834 |
69765 |
0 |
0 |
T6 |
74485 |
74429 |
0 |
0 |
T7 |
1853 |
1769 |
0 |
0 |
T8 |
123927 |
77368 |
0 |
0 |
T9 |
114479 |
821747 |
0 |
0 |
T10 |
55372 |
31863 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
13331120 |
0 |
0 |
T4 |
380942 |
229051 |
0 |
0 |
T5 |
69834 |
0 |
0 |
0 |
T6 |
74485 |
0 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
0 |
0 |
0 |
T9 |
114479 |
124333 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T18 |
124780 |
0 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T41 |
0 |
45688 |
0 |
0 |
T42 |
0 |
75585 |
0 |
0 |
T43 |
250970 |
16924 |
0 |
0 |
T49 |
0 |
108211 |
0 |
0 |
T91 |
0 |
9602 |
0 |
0 |
T134 |
0 |
3260 |
0 |
0 |
T142 |
0 |
35618 |
0 |
0 |
T143 |
0 |
500622 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
168692 |
0 |
0 |
T4 |
380942 |
261 |
0 |
0 |
T5 |
69834 |
0 |
0 |
0 |
T6 |
74485 |
0 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
5 |
0 |
0 |
T9 |
114479 |
1033 |
0 |
0 |
T10 |
55372 |
113 |
0 |
0 |
T18 |
124780 |
0 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T35 |
0 |
32 |
0 |
0 |
T38 |
0 |
15 |
0 |
0 |
T43 |
250970 |
632 |
0 |
0 |
T44 |
0 |
107 |
0 |
0 |
T51 |
0 |
52 |
0 |
0 |
T63 |
0 |
115 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
168692 |
0 |
0 |
T4 |
380942 |
261 |
0 |
0 |
T5 |
69834 |
0 |
0 |
0 |
T6 |
74485 |
0 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
5 |
0 |
0 |
T9 |
114479 |
1033 |
0 |
0 |
T10 |
55372 |
113 |
0 |
0 |
T18 |
124780 |
0 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T35 |
0 |
32 |
0 |
0 |
T38 |
0 |
15 |
0 |
0 |
T43 |
250970 |
632 |
0 |
0 |
T44 |
0 |
107 |
0 |
0 |
T51 |
0 |
52 |
0 |
0 |
T63 |
0 |
115 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T15,T16 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T5 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T81,T115,T153 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T81,T115,T153 |
1 | Covered | T2,T3,T5 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T81,T115,T153 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T15,T16 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T15,T16 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T15,T16 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T2,T3,T5 |
1 |
0 |
- |
Covered |
T2,T3,T5 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1441 |
1441 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1441 |
1441 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
405360363 |
0 |
0 |
T1 |
31260 |
31200 |
0 |
0 |
T2 |
95782 |
95691 |
0 |
0 |
T3 |
56406 |
56355 |
0 |
0 |
T4 |
380942 |
380847 |
0 |
0 |
T5 |
69834 |
69765 |
0 |
0 |
T6 |
74485 |
74429 |
0 |
0 |
T7 |
1853 |
1769 |
0 |
0 |
T8 |
123927 |
123919 |
0 |
0 |
T9 |
114479 |
114421 |
0 |
0 |
T10 |
55372 |
55311 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
230487461 |
0 |
0 |
T1 |
31260 |
31200 |
0 |
0 |
T2 |
95782 |
48501 |
0 |
0 |
T3 |
56406 |
2395 |
0 |
0 |
T4 |
380942 |
380847 |
0 |
0 |
T5 |
69834 |
37983 |
0 |
0 |
T6 |
74485 |
74429 |
0 |
0 |
T7 |
1853 |
1769 |
0 |
0 |
T8 |
123927 |
123919 |
0 |
0 |
T9 |
114479 |
114421 |
0 |
0 |
T10 |
55372 |
55311 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
35 |
0 |
0 |
T15 |
187321 |
27 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
T74 |
210794 |
0 |
0 |
0 |
T144 |
128010 |
0 |
0 |
0 |
T145 |
192677 |
0 |
0 |
0 |
T146 |
84495 |
0 |
0 |
0 |
T147 |
59077 |
0 |
0 |
0 |
T148 |
129924 |
0 |
0 |
0 |
T149 |
992331 |
0 |
0 |
0 |
T150 |
108801 |
0 |
0 |
0 |
T151 |
16336 |
0 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
165740 |
0 |
0 |
T2 |
95782 |
334 |
0 |
0 |
T3 |
56406 |
288 |
0 |
0 |
T4 |
380942 |
0 |
0 |
0 |
T5 |
69834 |
231 |
0 |
0 |
T6 |
74485 |
0 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
0 |
0 |
0 |
T9 |
114479 |
0 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T11 |
0 |
82 |
0 |
0 |
T12 |
0 |
142 |
0 |
0 |
T17 |
0 |
890 |
0 |
0 |
T18 |
0 |
733 |
0 |
0 |
T19 |
0 |
744 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T25 |
0 |
193 |
0 |
0 |
T34 |
0 |
547 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
165740 |
0 |
0 |
T2 |
95782 |
334 |
0 |
0 |
T3 |
56406 |
288 |
0 |
0 |
T4 |
380942 |
0 |
0 |
0 |
T5 |
69834 |
231 |
0 |
0 |
T6 |
74485 |
0 |
0 |
0 |
T7 |
1853 |
0 |
0 |
0 |
T8 |
123927 |
0 |
0 |
0 |
T9 |
114479 |
0 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T11 |
0 |
82 |
0 |
0 |
T12 |
0 |
142 |
0 |
0 |
T17 |
0 |
890 |
0 |
0 |
T18 |
0 |
733 |
0 |
0 |
T19 |
0 |
744 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T25 |
0 |
193 |
0 |
0 |
T34 |
0 |
547 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 44 | 86.27 |
Logical | 51 | 44 | 86.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T64,T35 |
1 | 1 | Covered | T4,T8,T9 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T41,T76,T77 |
1 | 1 | Covered | T9,T43,T64 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T43,T64 |
1 | 1 | Covered | T9,T43,T64 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T43,T64 |
1 | 1 | Covered | T9,T43,T64 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T9,T43,T64 |
0 | 1 | Covered | T9,T43,T64 |
1 | 0 | Covered | T41,T76,T77 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T41,T76,T77 |
1 | Covered | T9,T43,T64 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T41,T76,T77 |
0 | 1 | Covered | T9,T43,T64 |
1 | 0 | Covered | T9,T43,T64 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T43,T64 |
1 | 1 | Covered | T9,T43,T64 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T43,T64 |
1 | 1 | Covered | T9,T43,T64 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T43,T64 |
1 | 1 | Covered | T9,T43,T64 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T9,T43,T64 |
1 | 1 | Covered | T9,T43,T64 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T43,T64 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T9,T43,T64 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T9,T43,T64 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T43,T64 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T43,T64 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T43,T64 |
1 | 0 | Covered | T141 |
1 | 1 | Covered | T9,T43,T64 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T43,T64 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T9,T43,T64 |
1 |
0 |
- |
Covered |
T9,T43,T64 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1441 |
1441 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1441 |
1441 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
405360363 |
0 |
0 |
T1 |
31260 |
31200 |
0 |
0 |
T2 |
95782 |
95691 |
0 |
0 |
T3 |
56406 |
56355 |
0 |
0 |
T4 |
380942 |
380847 |
0 |
0 |
T5 |
69834 |
69765 |
0 |
0 |
T6 |
74485 |
74429 |
0 |
0 |
T7 |
1853 |
1769 |
0 |
0 |
T8 |
123927 |
123919 |
0 |
0 |
T9 |
114479 |
114421 |
0 |
0 |
T10 |
55372 |
55311 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
370241247 |
0 |
0 |
T1 |
31260 |
31200 |
0 |
0 |
T2 |
95782 |
95691 |
0 |
0 |
T3 |
56406 |
56355 |
0 |
0 |
T4 |
380942 |
380847 |
0 |
0 |
T5 |
69834 |
69765 |
0 |
0 |
T6 |
74485 |
74429 |
0 |
0 |
T7 |
1853 |
1769 |
0 |
0 |
T8 |
123927 |
123919 |
0 |
0 |
T9 |
114479 |
704981 |
0 |
0 |
T10 |
55372 |
55311 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
538888 |
0 |
0 |
T9 |
114479 |
7068 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T11 |
26729 |
0 |
0 |
0 |
T18 |
124780 |
0 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T32 |
62584 |
0 |
0 |
0 |
T35 |
0 |
25704 |
0 |
0 |
T38 |
635197 |
0 |
0 |
0 |
T40 |
0 |
3028 |
0 |
0 |
T43 |
250970 |
57 |
0 |
0 |
T44 |
53395 |
0 |
0 |
0 |
T63 |
60621 |
0 |
0 |
0 |
T64 |
0 |
2533 |
0 |
0 |
T88 |
0 |
10 |
0 |
0 |
T91 |
0 |
41 |
0 |
0 |
T92 |
0 |
2736 |
0 |
0 |
T96 |
0 |
4 |
0 |
0 |
T142 |
0 |
58 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
173560 |
0 |
0 |
T9 |
114479 |
2360 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T11 |
26729 |
0 |
0 |
0 |
T18 |
124780 |
0 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T32 |
62584 |
0 |
0 |
0 |
T38 |
635197 |
0 |
0 |
0 |
T40 |
0 |
1736 |
0 |
0 |
T41 |
0 |
1798 |
0 |
0 |
T42 |
0 |
3311 |
0 |
0 |
T43 |
250970 |
94 |
0 |
0 |
T44 |
53395 |
0 |
0 |
0 |
T63 |
60621 |
0 |
0 |
0 |
T64 |
0 |
744 |
0 |
0 |
T91 |
0 |
85 |
0 |
0 |
T92 |
0 |
806 |
0 |
0 |
T118 |
0 |
1054 |
0 |
0 |
T142 |
0 |
84 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405539758 |
173560 |
0 |
0 |
T9 |
114479 |
2360 |
0 |
0 |
T10 |
55372 |
0 |
0 |
0 |
T11 |
26729 |
0 |
0 |
0 |
T18 |
124780 |
0 |
0 |
0 |
T20 |
52630 |
0 |
0 |
0 |
T32 |
62584 |
0 |
0 |
0 |
T38 |
635197 |
0 |
0 |
0 |
T40 |
0 |
1736 |
0 |
0 |
T41 |
0 |
1798 |
0 |
0 |
T42 |
0 |
3311 |
0 |
0 |
T43 |
250970 |
94 |
0 |
0 |
T44 |
53395 |
0 |
0 |
0 |
T63 |
60621 |
0 |
0 |
0 |
T64 |
0 |
744 |
0 |
0 |
T91 |
0 |
85 |
0 |
0 |
T92 |
0 |
806 |
0 |
0 |
T118 |
0 |
1054 |
0 |
0 |
T142 |
0 |
84 |
0 |
0 |