Module Definition
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Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 81.82 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_fmt_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31



Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 81.82 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.57 100.00 86.27 100.00 100.00 u_rx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31



Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 81.82 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.12 100.00 76.47 100.00 100.00 u_tx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31



Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 81.82 95.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_acq_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 94.10 100.00 90.00 92.31



Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.79 100.00 79.17 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.16 100.00 88.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.57 100.00 86.27 100.00 100.00 u_rx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.79 100.00 79.17 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.16 100.00 88.64 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.12 100.00 76.47 100.00 100.00 u_tx_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_fmt_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.59 100.00 82.35 100.00 100.00 u_acq_fifo_sram_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T8,T9
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 500159003 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2147483647 500159003 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 500159003 0 0
T1 125040 28022 0 0
T2 383128 52271 0 0
T3 225624 54634 0 0
T4 3047536 379508 0 0
T5 558672 39294 0 0
T6 595880 1831 0 0
T7 14824 0 0 0
T8 991416 125892 0 0
T9 915832 585773 0 0
T10 442976 54696 0 0
T11 0 12385 0 0
T18 499120 122248 0 0
T20 210520 580 0 0
T25 0 27 0 0
T32 0 58950 0 0
T33 0 18842 0 0
T38 0 634171 0 0
T43 1003880 286263 0 0
T44 0 50162 0 0
T51 0 230460 0 0
T63 0 57950 0 0
T64 0 289471 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 250080 249600 0 0
T2 766256 765528 0 0
T3 451248 450840 0 0
T4 3047536 3046776 0 0
T5 558672 558120 0 0
T6 595880 595432 0 0
T7 14824 14152 0 0
T8 991416 991352 0 0
T9 915832 915368 0 0
T10 442976 442488 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 250080 249600 0 0
T2 766256 765528 0 0
T3 451248 450840 0 0
T4 3047536 3046776 0 0
T5 558672 558120 0 0
T6 595880 595432 0 0
T7 14824 14152 0 0
T8 991416 991352 0 0
T9 915832 915368 0 0
T10 442976 442488 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 250080 249600 0 0
T2 766256 765528 0 0
T3 451248 450840 0 0
T4 3047536 3046776 0 0
T5 558672 558120 0 0
T6 595880 595432 0 0
T7 14824 14152 0 0
T8 991416 991352 0 0
T9 915832 915368 0 0
T10 442976 442488 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 500159003 0 0
T1 125040 28022 0 0
T2 383128 52271 0 0
T3 225624 54634 0 0
T4 3047536 379508 0 0
T5 558672 39294 0 0
T6 595880 1831 0 0
T7 14824 0 0 0
T8 991416 125892 0 0
T9 915832 585773 0 0
T10 442976 54696 0 0
T11 0 12385 0 0
T18 499120 122248 0 0
T20 210520 580 0 0
T25 0 27 0 0
T32 0 58950 0 0
T33 0 18842 0 0
T38 0 634171 0 0
T43 1003880 286263 0 0
T44 0 50162 0 0
T51 0 230460 0 0
T63 0 57950 0 0
T64 0 289471 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T43,T44
110Not Covered
111CoveredT4,T8,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T8,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4,T8,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT9,T43,T44
10CoveredT4,T8,T9
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T8,T9
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T8,T9


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T8,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_inp_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 405539758 206691 0 0
DepthKnown_A 405539758 405360363 0 0
RvalidKnown_A 405539758 405360363 0 0
WreadyKnown_A 405539758 405360363 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 405539758 206691 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 206691 0 0
T4 380942 267 0 0
T5 69834 0 0 0
T6 74485 0 0 0
T7 1853 0 0 0
T8 123927 9 0 0
T9 114479 1327 0 0
T10 55372 153 0 0
T18 124780 0 0 0
T20 52630 0 0 0
T38 0 21 0 0
T43 250970 658 0 0
T44 0 126 0 0
T51 0 138 0 0
T63 0 159 0 0
T64 0 24 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 206691 0 0
T4 380942 267 0 0
T5 69834 0 0 0
T6 74485 0 0 0
T7 1853 0 0 0
T8 123927 9 0 0
T9 114479 1327 0 0
T10 55372 153 0 0
T18 124780 0 0 0
T20 52630 0 0 0
T38 0 21 0 0
T43 250970 658 0 0
T44 0 126 0 0
T51 0 138 0 0
T63 0 159 0 0
T64 0 24 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T43,T91
110Not Covered
111CoveredT4,T8,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T8,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4,T8,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT9,T43,T91
10CoveredT4,T8,T9
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T8,T9
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T8,T9


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T8,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_inp_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 405539758 386678 0 0
DepthKnown_A 405539758 405360363 0 0
RvalidKnown_A 405539758 405360363 0 0
WreadyKnown_A 405539758 405360363 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 405539758 386678 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 386678 0 0
T4 380942 58 0 0
T5 69834 0 0 0
T6 74485 0 0 0
T7 1853 0 0 0
T8 123927 275 0 0
T9 114479 4350 0 0
T10 55372 117 0 0
T18 124780 0 0 0
T20 52630 0 0 0
T38 0 256 0 0
T43 250970 641 0 0
T44 0 60 0 0
T51 0 1029 0 0
T63 0 124 0 0
T64 0 768 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 386678 0 0
T4 380942 58 0 0
T5 69834 0 0 0
T6 74485 0 0 0
T7 1853 0 0 0
T8 123927 275 0 0
T9 114479 4350 0 0
T10 55372 117 0 0
T18 124780 0 0 0
T20 52630 0 0 0
T38 0 256 0 0
T43 250970 641 0 0
T44 0 60 0 0
T51 0 1029 0 0
T63 0 124 0 0
T64 0 768 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT6,T34,T81
110Not Covered
111CoveredT1,T2,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT6,T34,T81
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_inp_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 405539758 273286 0 0
DepthKnown_A 405539758 405360363 0 0
RvalidKnown_A 405539758 405360363 0 0
WreadyKnown_A 405539758 405360363 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 405539758 273286 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 273286 0 0
T1 31260 144 0 0
T2 95782 260 0 0
T3 56406 0 0 0
T4 380942 0 0 0
T5 69834 203 0 0
T6 74485 206 0 0
T7 1853 0 0 0
T8 123927 0 0 0
T9 114479 0 0 0
T10 55372 0 0 0
T11 0 80 0 0
T20 0 278 0 0
T25 0 27 0 0
T32 0 297 0 0
T33 0 119 0 0
T34 0 1132 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 273286 0 0
T1 31260 144 0 0
T2 95782 260 0 0
T3 56406 0 0 0
T4 380942 0 0 0
T5 69834 203 0 0
T6 74485 206 0 0
T7 1853 0 0 0
T8 123927 0 0 0
T9 114479 0 0 0
T10 55372 0 0 0
T11 0 80 0 0
T20 0 278 0 0
T25 0 27 0 0
T32 0 297 0 0
T33 0 119 0 0
T34 0 1132 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT34,T81,T82
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT34,T81,T82
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_inp_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 405539758 249728 0 0
DepthKnown_A 405539758 405360363 0 0
RvalidKnown_A 405539758 405360363 0 0
WreadyKnown_A 405539758 405360363 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 405539758 249728 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 249728 0 0
T1 31260 22 0 0
T2 95782 388 0 0
T3 56406 290 0 0
T4 380942 0 0 0
T5 69834 279 0 0
T6 74485 222 0 0
T7 1853 0 0 0
T8 123927 0 0 0
T9 114479 0 0 0
T10 55372 0 0 0
T11 0 97 0 0
T18 0 739 0 0
T20 0 36 0 0
T32 0 38 0 0
T33 0 19 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 249728 0 0
T1 31260 22 0 0
T2 95782 388 0 0
T3 56406 290 0 0
T4 380942 0 0 0
T5 69834 279 0 0
T6 74485 222 0 0
T7 1853 0 0 0
T8 123927 0 0 0
T9 114479 0 0 0
T10 55372 0 0 0
T11 0 97 0 0
T18 0 739 0 0
T20 0 36 0 0
T32 0 38 0 0
T33 0 19 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf
TotalCoveredPercent
Conditions241979.17
Logical241979.17
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT9,T43,T64
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T8,T9
110Not Covered
111CoveredT4,T8,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T8,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT9,T43,T64
10CoveredT1,T2,T3
11CoveredT4,T8,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT4,T8,T9
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T8,T9
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T8,T9


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T8,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter.u_oup_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 405539758 40526020 0 0
DepthKnown_A 405539758 405360363 0 0
RvalidKnown_A 405539758 405360363 0 0
WreadyKnown_A 405539758 405360363 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 405539758 40526020 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 40526020 0 0
T4 380942 1267 0 0
T5 69834 0 0 0
T6 74485 0 0 0
T7 1853 0 0 0
T8 123927 1833 0 0
T9 114479 468371 0 0
T10 55372 1322 0 0
T18 124780 0 0 0
T20 52630 0 0 0
T38 0 1756 0 0
T43 250970 38298 0 0
T44 0 408 0 0
T51 0 31949 0 0
T63 0 3939 0 0
T64 0 150252 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 40526020 0 0
T4 380942 1267 0 0
T5 69834 0 0 0
T6 74485 0 0 0
T7 1853 0 0 0
T8 123927 1833 0 0
T9 114479 468371 0 0
T10 55372 1322 0 0
T18 124780 0 0 0
T20 52630 0 0 0
T38 0 1756 0 0
T43 250970 38298 0 0
T44 0 408 0 0
T51 0 31949 0 0
T63 0 3939 0 0
T64 0 150252 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf
TotalCoveredPercent
Conditions241979.17
Logical241979.17
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT1,T2,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter.u_oup_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 405539758 110059372 0 0
DepthKnown_A 405539758 405360363 0 0
RvalidKnown_A 405539758 405360363 0 0
WreadyKnown_A 405539758 405360363 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 405539758 110059372 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 110059372 0 0
T1 31260 29003 0 0
T2 95782 38294 0 0
T3 56406 0 0 0
T4 380942 0 0 0
T5 69834 30481 0 0
T6 74485 71066 0 0
T7 1853 0 0 0
T8 123927 0 0 0
T9 114479 0 0 0
T10 55372 0 0 0
T11 0 10987 0 0
T20 0 45881 0 0
T25 0 5751 0 0
T32 0 61147 0 0
T33 0 21134 0 0
T34 0 463227 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 110059372 0 0
T1 31260 29003 0 0
T2 95782 38294 0 0
T3 56406 0 0 0
T4 380942 0 0 0
T5 69834 30481 0 0
T6 74485 71066 0 0
T7 1853 0 0 0
T8 123927 0 0 0
T9 114479 0 0 0
T10 55372 0 0 0
T11 0 10987 0 0
T20 0 45881 0 0
T25 0 5751 0 0
T32 0 61147 0 0
T33 0 21134 0 0
T34 0 463227 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT35,T36,T37
101CoveredT4,T8,T9
110Not Covered
111CoveredT4,T8,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T8,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT1,T2,T3
11CoveredT4,T8,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT4,T8,T9
10CoveredT4,T8,T9
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T8,T9
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T4,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T8,T9


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T8,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter.u_oup_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 405539758 145330895 0 0
DepthKnown_A 405539758 405360363 0 0
RvalidKnown_A 405539758 405360363 0 0
WreadyKnown_A 405539758 405360363 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 405539758 145330895 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 145330895 0 0
T4 380942 377916 0 0
T5 69834 0 0 0
T6 74485 0 0 0
T7 1853 0 0 0
T8 123927 123775 0 0
T9 114479 111725 0 0
T10 55372 53104 0 0
T18 124780 0 0 0
T20 52630 0 0 0
T38 0 632138 0 0
T43 250970 246666 0 0
T44 0 49568 0 0
T51 0 197344 0 0
T63 0 53728 0 0
T64 0 138427 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 145330895 0 0
T4 380942 377916 0 0
T5 69834 0 0 0
T6 74485 0 0 0
T7 1853 0 0 0
T8 123927 123775 0 0
T9 114479 111725 0 0
T10 55372 53104 0 0
T18 124780 0 0 0
T20 52630 0 0 0
T38 0 632138 0 0
T43 250970 246666 0 0
T44 0 49568 0 0
T51 0 197344 0 0
T63 0 53728 0 0
T64 0 138427 0 0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf
TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT81,T82,T115
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (13'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter.u_oup_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 405539758 203126333 0 0
DepthKnown_A 405539758 405360363 0 0
RvalidKnown_A 405539758 405360363 0 0
WreadyKnown_A 405539758 405360363 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 405539758 203126333 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 203126333 0 0
T1 31260 27856 0 0
T2 95782 51623 0 0
T3 56406 54344 0 0
T4 380942 0 0 0
T5 69834 38812 0 0
T6 74485 1403 0 0
T7 1853 0 0 0
T8 123927 0 0 0
T9 114479 0 0 0
T10 55372 0 0 0
T11 0 12208 0 0
T18 0 121509 0 0
T20 0 266 0 0
T32 0 58615 0 0
T33 0 18704 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 405360363 0 0
T1 31260 31200 0 0
T2 95782 95691 0 0
T3 56406 56355 0 0
T4 380942 380847 0 0
T5 69834 69765 0 0
T6 74485 74429 0 0
T7 1853 1769 0 0
T8 123927 123919 0 0
T9 114479 114421 0 0
T10 55372 55311 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 405539758 203126333 0 0
T1 31260 27856 0 0
T2 95782 51623 0 0
T3 56406 54344 0 0
T4 380942 0 0 0
T5 69834 38812 0 0
T6 74485 1403 0 0
T7 1853 0 0 0
T8 123927 0 0 0
T9 114479 0 0 0
T10 55372 0 0 0
T11 0 12208 0 0
T18 0 121509 0 0
T20 0 266 0 0
T32 0 58615 0 0
T33 0 18704 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%