Group : i2c_env_pkg::i2c_operating_mode_cg
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Group : i2c_env_pkg::i2c_operating_mode_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
0.00 0.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.openting_mode_cg 0.00 1 100 1 64 64




Group Instance : i2c_env_pkg.openting_mode_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.openting_mode_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 14 0 0.00
Crosses 14 14 0 0.00


Variables for Group Instance i2c_env_pkg.openting_mode_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ip_mode 2 2 0 0.00 100 1 1 0
cp_scl_frequency 6 6 0 0.00 100 1 1 0
cp_tb_mode 2 2 0 0.00 100 1 1 0
ip_mode 2 2 0 0.00 100 1 1 2
tb_mode 2 2 0 0.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.openting_mode_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_mode_cross 2 2 0 0.00 100 1 1 0
cp_ip_mode_x_frequency 12 12 0 0.00 100 1 1 0


Summary for Variable cp_ip_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_ip_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
target 0 1 1
host 0 1 1



Summary for Variable cp_scl_frequency

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 6 0 0.00


User Defined Bins for cp_scl_frequency

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
fast_plus_mode[0] 0 1 1
fast_plus_mode[1] 0 1 1
fast_mode[0] 0 1 1
fast_mode[1] 0 1 1
standard_mode[0] 0 1 1
standard_mode[1] 0 1 1



Summary for Variable cp_tb_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_tb_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
target 0 1 1
host 0 1 1



Summary for Variable ip_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for ip_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable tb_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for tb_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross cp_mode_cross

Samples crossed: ip_mode tb_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 2 2 0 0.00


User Defined Cross Bins for cp_mode_cross

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
dut_host_tb_target 0 1 1
dut_target_tb_host 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
both_host 0 Excluded
both_target 0 Excluded



Summary for Cross cp_ip_mode_x_frequency

Samples crossed: cp_ip_mode cp_scl_frequency
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 12 0 0.00 12


Automatically Generated Cross Bins for cp_ip_mode_x_frequency

Uncovered bins
cp_ip_modecp_scl_frequencyCOUNTAT LEASTNUMBERSTATUS
* * -- -- 12

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