Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
19.05 19.05 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_rd_wr_cg 19.05 1 100 1 64 64




Group Instance : i2c_rd_wr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
19.05 1 100 1 64 64




Summary for Group Instance i2c_rd_wr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 14 4 22.22
Crosses 24 20 4 16.67


Variables for Group Instance i2c_rd_wr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
address_match 2 0 2 100.00 100 1 1 2
cp_address_match 4 4 0 0.00 100 1 1 0
cp_read_byte 5 5 0 0.00 100 1 1 0
cp_write_byte 5 5 0 0.00 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0


Crosses for Group Instance i2c_rd_wr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_address_match_x_ip_mode 4 0 4 100.00 100 1 1 0
cross_write_byte_x_ip_mode 10 10 0 0.00 100 1 1 0
cross_read_byte_x_ip_mode 10 10 0 0.00 100 1 1 0


Summary for Variable address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for address_match

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 174 1 T2 1 T9 8 T37 1
auto[1] 158 1 T10 9 T11 4 T37 4



Summary for Variable cp_address_match

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 4 0 0.00


User Defined Bins for cp_address_match

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_addr_no_match 0 1 1
read_addr_match 0 1 1
write_addr_no_match 0 1 1
write_addr_match 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal
ignore 0 Excluded



Summary for Variable cp_read_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 5 0 0.00


User Defined Bins for cp_read_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1
high 0 1 1
med 0 1 1
low 0 1 1
all_zero 0 1 1



Summary for Variable cp_write_byte

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 5 0 0.00


User Defined Bins for cp_write_byte

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_one 0 1 1
high 0 1 1
med 0 1 1
low 0 1 1
all_zero 0 1 1



Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 178 1 T9 8 T10 7 T11 4
host 154 1 T2 1 T10 2 T37 1



Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins
address_matchip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] device 80 1 T9 8 T25 1 T17 1
auto[0] host 94 1 T2 1 T37 1 T28 4
auto[1] device 98 1 T10 7 T11 4 T37 4
auto[1] host 60 1 T10 2 T25 1 T18 2



Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 10 0 0.00 10


Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Uncovered bins
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 10



Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 10 0 0.00 10


Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Uncovered bins
cp_write_byteip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 10

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