Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26139	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38634

1

T1

616

T2

35

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34715	1			T1	163		T2	27		T3	20
values[0x0]	14672	1			T1	237		T2	17		T3	11
values[0x1]	15386	1			T1	236		T2	14		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46581

1

T1

630

T2

40

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	229	1			T1	4		T6	2		T7	3
valid_sources[0x01]	227	1			T7	1		T15	1		T11	5
valid_sources[0x02]	244	1			T3	1		T7	1		T26	18
valid_sources[0x03]	327	1			T2	2		T3	3		T7	5
valid_sources[0x04]	186	1			T7	1		T4	1		T5	1
valid_sources[0x05]	363	1			T6	1		T7	2		T37	2
valid_sources[0x06]	333	1			T6	7		T9	7		T37	1
valid_sources[0x07]	213	1			T6	18		T26	20		T16	1
valid_sources[0x08]	370	1			T1	13		T15	1		T16	1
valid_sources[0x09]	254	1			T1	8		T26	26		T16	1
valid_sources[0x0a]	235	1			T6	3		T7	2		T16	1
valid_sources[0x0b]	238	1			T26	11		T16	1		T11	3
valid_sources[0x0c]	378	1			T1	13		T15	2		T16	1
valid_sources[0x0d]	194	1			T6	2		T7	2		T12	1
valid_sources[0x0e]	389	1			T7	2		T12	1		T9	30
valid_sources[0x0f]	203	1			T1	5		T6	13		T37	1
valid_sources[0x10]	199	1			T7	2		T12	2		T9	7
valid_sources[0x11]	216	1			T3	1		T6	2		T10	1
valid_sources[0x12]	199	1			T14	1		T26	24		T16	1
valid_sources[0x13]	240	1			T6	15		T12	3		T16	3
valid_sources[0x14]	236	1			T2	2		T7	2		T11	6
valid_sources[0x15]	258	1			T6	2		T9	4		T37	1
valid_sources[0x16]	262	1			T8	4		T7	2		T15	1
valid_sources[0x17]	465	1			T2	1		T7	1		T15	1
valid_sources[0x18]	192	1			T6	9		T7	4		T10	28
valid_sources[0x19]	229	1			T3	1		T7	3		T10	23
valid_sources[0x1a]	205	1			T13	2		T10	11		T16	4
valid_sources[0x1b]	205	1			T1	4		T7	2		T16	1
valid_sources[0x1c]	294	1			T6	8		T26	5		T16	2
valid_sources[0x1d]	478	1			T9	12		T10	9		T26	7
valid_sources[0x1e]	190	1			T2	2		T6	4		T7	2
valid_sources[0x1f]	192	1			T7	1		T26	1		T16	2
valid_sources[0x20]	289	1			T6	4		T7	1		T11	2
valid_sources[0x21]	314	1			T15	1		T16	1		T4	2
valid_sources[0x22]	256	1			T1	6		T10	4		T16	2
valid_sources[0x23]	243	1			T6	9		T7	2		T14	1
valid_sources[0x24]	206	1			T7	1		T10	15		T11	6
valid_sources[0x25]	359	1			T6	14		T8	2		T26	6
valid_sources[0x26]	205	1			T2	1		T7	4		T9	6
valid_sources[0x27]	220	1			T6	2		T26	2		T16	1
valid_sources[0x28]	259	1			T6	1		T7	1		T13	2
valid_sources[0x29]	275	1			T1	12		T3	1		T10	7
valid_sources[0x2a]	197	1			T1	4		T16	1		T43	1
valid_sources[0x2b]	270	1			T6	5		T7	2		T4	2
valid_sources[0x2c]	195	1			T2	2		T6	2		T7	1
valid_sources[0x2d]	223	1			T2	1		T7	4		T15	1
valid_sources[0x2e]	442	1			T6	5		T13	1		T10	8
valid_sources[0x2f]	326	1			T6	3		T10	19		T11	4
valid_sources[0x30]	234	1			T11	4		T37	3		T27	17
valid_sources[0x31]	248	1			T1	7		T10	27		T16	1
valid_sources[0x32]	357	1			T1	9		T6	3		T12	1
valid_sources[0x33]	203	1			T1	11		T2	3		T7	1
valid_sources[0x34]	232	1			T16	1		T11	3		T4	2
valid_sources[0x35]	204	1			T1	1		T15	1		T16	2
valid_sources[0x36]	278	1			T3	1		T6	4		T9	13
valid_sources[0x37]	216	1			T1	7		T7	1		T26	1
valid_sources[0x38]	195	1			T1	4		T2	2		T3	1
valid_sources[0x39]	234	1			T6	2		T7	2		T10	12
valid_sources[0x3a]	193	1			T6	4		T7	3		T9	6
valid_sources[0x3b]	250	1			T2	1		T3	1		T6	6
valid_sources[0x3c]	209	1			T7	1		T43	1		T37	1
valid_sources[0x3d]	275	1			T1	25		T6	2		T10	3
valid_sources[0x3e]	181	1			T1	11		T6	3		T9	1
valid_sources[0x3f]	202	1			T1	4		T7	1		T26	5
valid_sources[0x40]	199	1			T12	1		T13	1		T16	1
valid_sources[0x41]	170	1			T7	1		T14	1		T10	11
valid_sources[0x42]	260	1			T7	2		T9	24		T26	5
valid_sources[0x43]	312	1			T6	9		T7	1		T10	9
valid_sources[0x44]	309	1			T1	1		T2	1		T3	1
valid_sources[0x45]	262	1			T2	1		T26	7		T16	2
valid_sources[0x46]	222	1			T1	7		T2	1		T7	4
valid_sources[0x47]	469	1			T1	17		T9	8		T16	1
valid_sources[0x48]	279	1			T7	1		T12	3		T10	9
valid_sources[0x49]	278	1			T1	5		T7	1		T15	1
valid_sources[0x4a]	233	1			T1	4		T7	1		T9	4
valid_sources[0x4b]	194	1			T6	3		T7	1		T12	1
valid_sources[0x4c]	178	1			T6	20		T7	3		T16	1
valid_sources[0x4d]	367	1			T6	6		T7	4		T9	4
valid_sources[0x4e]	205	1			T7	1		T4	2		T37	4
valid_sources[0x4f]	247	1			T10	25		T26	8		T16	1
valid_sources[0x50]	219	1			T26	1		T16	1		T37	1
valid_sources[0x51]	187	1			T3	1		T13	1		T15	1
valid_sources[0x52]	201	1			T6	1		T13	2		T14	2
valid_sources[0x53]	201	1			T9	7		T26	3		T11	2
valid_sources[0x54]	244	1			T6	28		T14	1		T10	4
valid_sources[0x55]	220	1			T2	1		T6	4		T11	5
valid_sources[0x56]	218	1			T1	2		T6	4		T16	1
valid_sources[0x57]	227	1			T1	12		T7	3		T9	3
valid_sources[0x58]	278	1			T1	7		T2	1		T6	4
valid_sources[0x59]	322	1			T9	24		T10	34		T26	22
valid_sources[0x5a]	370	1			T7	1		T5	2		T29	4
valid_sources[0x5b]	399	1			T10	1		T37	1		T27	3
valid_sources[0x5c]	287	1			T1	15		T7	1		T10	10
valid_sources[0x5d]	380	1			T2	1		T9	6		T27	5
valid_sources[0x5e]	252	1			T2	1		T7	1		T12	1
valid_sources[0x5f]	337	1			T1	3		T10	6		T16	2
valid_sources[0x60]	209	1			T2	1		T7	1		T16	1
valid_sources[0x61]	229	1			T6	9		T7	2		T13	1
valid_sources[0x62]	328	1			T12	1		T28	4		T29	2
valid_sources[0x63]	156	1			T6	3		T7	1		T26	13
valid_sources[0x64]	236	1			T1	50		T6	20		T26	9
valid_sources[0x65]	196	1			T7	1		T16	1		T11	2
valid_sources[0x66]	256	1			T6	5		T13	1		T16	1
valid_sources[0x67]	215	1			T1	7		T26	15		T16	2
valid_sources[0x68]	327	1			T2	2		T11	1		T37	2
valid_sources[0x69]	197	1			T2	2		T3	1		T6	1
valid_sources[0x6a]	252	1			T1	11		T7	1		T11	1
valid_sources[0x6b]	183	1			T1	8		T15	1		T26	10
valid_sources[0x6c]	169	1			T2	1		T7	1		T26	5
valid_sources[0x6d]	198	1			T6	2		T7	1		T11	1
valid_sources[0x6e]	308	1			T6	2		T7	1		T9	33
valid_sources[0x6f]	266	1			T12	2		T10	27		T15	1
valid_sources[0x70]	241	1			T7	1		T15	2		T37	2
valid_sources[0x71]	216	1			T6	3		T7	2		T12	1
valid_sources[0x72]	214	1			T2	1		T6	3		T7	1
valid_sources[0x73]	190	1			T1	8		T2	1		T16	4
valid_sources[0x74]	201	1			T9	6		T26	16		T16	1
valid_sources[0x75]	253	1			T1	7		T6	11		T11	6
valid_sources[0x76]	349	1			T2	1		T3	1		T6	6
valid_sources[0x77]	253	1			T2	1		T6	4		T9	16
valid_sources[0x78]	275	1			T2	1		T7	3		T14	1
valid_sources[0x79]	191	1			T1	16		T10	3		T37	1
valid_sources[0x7a]	204	1			T7	3		T43	1		T37	1
valid_sources[0x7b]	254	1			T1	3		T9	7		T16	1
valid_sources[0x7c]	252	1			T1	1		T3	2		T6	2
valid_sources[0x7d]	338	1			T1	4		T7	1		T15	1
valid_sources[0x7e]	204	1			T6	4		T8	1		T7	2
valid_sources[0x7f]	224	1			T7	3		T10	9		T15	1
valid_sources[0x80]	370	1			T3	1		T6	1		T10	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14765

1

T1

162

T2

13

T3

12

values[0x0]

all_enables

biggest_size

12235

1

T1

236

T2

12

T3

9

values[0x1]

all_enables

biggest_size

11634

1

T1

218

T2

10

T3

1