Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.62	0.00	0.00	94.87				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	745229	0	0	0
ctrl_rd_A	745229	3082	0	0
host_fifo_config_rd_A	745229	1768	0	0
host_nack_handler_timeout_rd_A	745229	1856	0	0
host_timeout_ctrl_rd_A	745229	1755	0	0
intr_enable_rd_A	745229	4844	0	0
ovrd_rd_A	745229	2142	0	0
target_fifo_config_rd_A	745229	1968	0	0
target_id_rd_A	745229	2236	0	0
target_timeout_ctrl_rd_A	745229	1894	0	0
timeout_ctrl_rd_A	745229	2149	0	0
timing0_rd_A	745229	1946	0	0
timing1_rd_A	745229	2115	0	0
timing2_rd_A	745229	1968	0	0
timing3_rd_A	745229	1906	0	0
timing4_rd_A	745229	2049	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	3082	0	0
T4	0	6	0	0
T7	6959	19	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	5	0	0
T23	0	1	0	0
T26	5905	49	0	0
T27	0	236	0	0
T30	0	484	0	0
T31	0	214	0	0
T37	0	42	0	0
T45	0	8	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	1768	0	0
T4	0	3	0	0
T7	6959	25	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	6	0	0
T26	5905	45	0	0
T27	0	208	0	0
T30	0	409	0	0
T31	0	223	0	0
T32	0	3	0	0
T37	0	3	0	0
T45	0	3	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	1856	0	0
T4	0	6	0	0
T7	6959	31	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	4	0	0
T23	0	4	0	0
T26	5905	43	0	0
T27	0	226	0	0
T30	0	431	0	0
T31	0	227	0	0
T37	0	21	0	0
T45	0	9	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	1755	0	0
T4	0	9	0	0
T7	6959	10	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	10	0	0
T23	0	7	0	0
T26	5905	64	0	0
T27	0	230	0	0
T30	0	441	0	0
T31	0	239	0	0
T37	0	10	0	0
T45	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	4844	0	0
T3	1232	20	0	0
T4	0	13	0	0
T6	3186	0	0	0
T7	6959	0	0	0
T8	1768	0	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	14	0	0
T20	0	12	0	0
T26	0	49	0	0
T27	0	225	0	0
T30	0	451	0	0
T37	0	42	0	0
T38	0	13	0	0
T39	0	11	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	2142	0	0
T4	2765	5	0	0
T5	1514	0	0	0
T11	3479	0	0	0
T16	2791	0	0	0
T20	0	2	0	0
T26	5905	41	0	0
T27	13660	210	0	0
T28	1617	0	0	0
T30	0	452	0	0
T31	0	234	0	0
T32	0	5	0	0
T37	3508	39	0	0
T43	1074	0	0	0
T44	1773	0	0	0
T45	0	7	0	0
T46	0	22	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	1968	0	0
T4	0	16	0	0
T7	6959	2	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	9	0	0
T23	0	5	0	0
T26	5905	70	0	0
T27	0	223	0	0
T30	0	445	0	0
T31	0	223	0	0
T37	0	51	0	0
T45	0	1	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	2236	0	0
T4	0	3	0	0
T7	6959	27	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	24	0	0
T23	0	1	0	0
T26	5905	40	0	0
T27	0	246	0	0
T30	0	455	0	0
T31	0	213	0	0
T37	0	11	0	0
T45	0	18	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	1894	0	0
T4	0	5	0	0
T7	6959	15	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	3	0	0
T23	0	3	0	0
T26	5905	49	0	0
T27	0	193	0	0
T30	0	417	0	0
T31	0	242	0	0
T37	0	29	0	0
T45	0	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	2149	0	0
T4	0	2	0	0
T7	6959	5	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	20	0	0
T23	0	5	0	0
T26	5905	52	0	0
T27	0	231	0	0
T30	0	454	0	0
T31	0	243	0	0
T37	0	24	0	0
T45	0	17	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	1946	0	0
T4	0	4	0	0
T7	6959	28	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	7	0	0
T26	5905	79	0	0
T27	0	211	0	0
T30	0	474	0	0
T31	0	246	0	0
T37	0	39	0	0
T45	0	2	0	0
T46	0	53	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	2115	0	0
T4	0	9	0	0
T7	6959	12	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	5	0	0
T23	0	8	0	0
T26	5905	53	0	0
T27	0	258	0	0
T30	0	419	0	0
T31	0	233	0	0
T32	0	1	0	0
T45	0	11	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	1968	0	0
T4	0	11	0	0
T7	6959	10	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	9	0	0
T26	5905	64	0	0
T27	0	265	0	0
T30	0	458	0	0
T31	0	235	0	0
T32	0	7	0	0
T37	0	17	0	0
T45	0	10	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	1906	0	0
T4	0	10	0	0
T7	6959	17	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	11	0	0
T26	5905	54	0	0
T27	0	255	0	0
T30	0	439	0	0
T31	0	248	0	0
T32	0	5	0	0
T37	0	13	0	0
T45	0	8	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745229	2049	0	0
T4	0	4	0	0
T7	6959	16	0	0
T9	2233	0	0	0
T10	5362	0	0	0
T11	3479	0	0	0
T12	1735	0	0	0
T13	702	0	0	0
T14	846	0	0	0
T15	1375	0	0	0
T16	2791	0	0	0
T20	0	7	0	0
T23	0	12	0	0
T26	5905	52	0	0
T27	0	213	0	0
T30	0	463	0	0
T31	0	227	0	0
T37	0	27	0	0
T45	0	1	0	0