Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

162044

1

T4

200

T6

788

T10

65

ack

14585

1

T4

38

T6

13

T10

24

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	654	1			T4	1		T6	3		T10	1
high	36148	1			T4	49		T6	161		T10	17
med	65486	1			T4	90		T6	325		T10	29
sml	73725	1			T4	96		T6	310		T10	42
all_zero	616	1			T4	2		T6	2		T60	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88054

1

T4

120

T6

399

T10

39

auto[1]

88575

1

T4

118

T6

402

T10

50

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121421

1

T4

175

T6

528

T10

66

auto[1]

55208

1

T4

63

T6

273

T10

23

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168892

1

T4

222

T6

793

T10

79

auto[1]

7737

1

T4

16

T6

8

T10

10

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166658

1

T4

204

T6

788

T10

68

auto[1]

9971

1

T4

34

T6

13

T10

21

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167670

1

T4

205

T6

794

T10

69

auto[1]

8959

1

T4

33

T6

7

T10

20

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88054

1

T4

120

T6

399

T10

39

auto[1]

88575

1

T4

118

T6

402

T10

50

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121421

1

T4

175

T6

528

T10

66

auto[1]

55208

1

T4

63

T6

273

T10

23

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168892

1

T4

222

T6

793

T10

79

auto[1]

7737

1

T4

16

T6

8

T10

10

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166658

1

T4

204

T6

788

T10

68

auto[1]

9971

1

T4

34

T6

13

T10

21

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167670

1

T4

205

T6

794

T10

69

auto[1]

8959

1

T4

33

T6

7

T10

20

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

2

1

T33

1

T49

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T217

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T218

1

T50

1

T219

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

286

1

T4

5

T6

1

T10

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

136

1

T60

1

T39

2

T36

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

144

1

T10

1

T39

1

T36

3

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

524

1

T4

2

T6

1

T10

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

251

1

T4

2

T6

1

T38

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

239

1

T4

4

T6

1

T10

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

567

1

T4

5

T6

1

T10

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

290

1

T6

1

T60

1

T39

6

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

255

1

T4

1

T60

3

T39

6

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T98

1

T220

1

T221

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T36

1

T222

1

T223

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T36

1

T224

1

T46

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	51640	1			T4	54		T6	249		T10	15
write_address_byte	9971	1			T4	34		T6	13		T10	21
read_with_ack	2291	1			T6	4		T51	9		T38	1
read_with_nack	5446	1			T4	16		T6	4		T10	10
stop_byte	8959	1			T4	33		T6	7		T10	20
write_address_byte_nak	4894	1			T4	27		T6	12		T10	12
data_byte_nack	162044	1			T4	200		T6	788		T10	65
stop_byte_nack	5336	1			T4	26		T6	6		T10	13
nakok_byte_nack	81178	1			T4	94		T6	396		T10	36
nakok_addr_byte_nack	2411	1			T4	10		T6	6		T10	4