Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46493464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11168827

1

T1

68

T2

204

T3

163

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56684909	1			T1	187		T2	34079		T3	13885
values[0x0]	488026	1			T1	96		T2	105		T3	232
values[0x1]	489356	1			T1	86		T2	108		T3	248

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33207141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24455150

1

T1

132

T2

14821

T3

5469

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	228211	1			T1	1		T3	54		T6	3
valid_sources[0x01]	221422	1			T1	2		T3	54		T6	5
valid_sources[0x02]	186311	1			T3	70		T6	11		T7	3
valid_sources[0x03]	222855	1			T3	64		T6	5		T7	5
valid_sources[0x04]	204137	1			T1	1		T3	66		T6	8
valid_sources[0x05]	229097	1			T1	1		T3	51		T6	8
valid_sources[0x06]	198989	1			T1	3		T3	75		T6	3
valid_sources[0x07]	232591	1			T3	69		T6	6		T9	768
valid_sources[0x08]	220641	1			T1	8		T3	64		T6	4
valid_sources[0x09]	208905	1			T1	1		T3	43		T4	741
valid_sources[0x0a]	200054	1			T3	51		T6	6		T7	2
valid_sources[0x0b]	201240	1			T1	2		T3	49		T6	8
valid_sources[0x0c]	236714	1			T1	1		T3	56		T6	3
valid_sources[0x0d]	239669	1			T1	1		T3	44		T6	5
valid_sources[0x0e]	195557	1			T1	1		T2	14		T3	39
valid_sources[0x0f]	210272	1			T1	1		T3	55		T6	1
valid_sources[0x10]	203332	1			T1	1		T3	86		T6	7
valid_sources[0x11]	232609	1			T1	2		T2	3468		T3	71
valid_sources[0x12]	217762	1			T1	2		T3	68		T6	8
valid_sources[0x13]	215290	1			T1	1		T3	38		T4	445
valid_sources[0x14]	212525	1			T3	53		T6	3		T7	1
valid_sources[0x15]	232599	1			T3	53		T6	9		T7	1
valid_sources[0x16]	245885	1			T1	2		T3	48		T6	2
valid_sources[0x17]	205158	1			T1	3		T3	40		T6	7
valid_sources[0x18]	189144	1			T3	36		T6	10		T9	702
valid_sources[0x19]	225194	1			T1	1		T3	50		T6	5
valid_sources[0x1a]	206268	1			T1	2		T3	52		T4	668
valid_sources[0x1b]	199616	1			T2	16		T3	41		T6	6
valid_sources[0x1c]	199000	1			T3	52		T6	5		T9	728
valid_sources[0x1d]	211519	1			T1	1		T3	109		T6	10
valid_sources[0x1e]	203972	1			T1	3		T3	34		T6	7
valid_sources[0x1f]	253020	1			T3	65		T6	5		T7	6
valid_sources[0x20]	196298	1			T1	2		T2	3046		T3	73
valid_sources[0x21]	211002	1			T1	1		T3	46		T4	901
valid_sources[0x22]	206773	1			T1	3		T3	45		T6	7
valid_sources[0x23]	200955	1			T3	52		T6	4		T7	7
valid_sources[0x24]	211983	1			T1	1		T3	30		T6	6
valid_sources[0x25]	221612	1			T1	4		T2	18		T3	70
valid_sources[0x26]	213953	1			T1	2		T3	56		T4	52
valid_sources[0x27]	221930	1			T1	3		T2	872		T3	44
valid_sources[0x28]	208659	1			T1	1		T3	33		T6	5
valid_sources[0x29]	225367	1			T1	2		T3	37		T6	3
valid_sources[0x2a]	221488	1			T3	56		T6	7		T7	9
valid_sources[0x2b]	203569	1			T1	1		T3	59		T6	4
valid_sources[0x2c]	220617	1			T1	5		T3	66		T6	5
valid_sources[0x2d]	421008	1			T1	4		T3	54		T6	4
valid_sources[0x2e]	219955	1			T1	3		T3	84		T6	2
valid_sources[0x2f]	216885	1			T3	64		T6	7		T7	1
valid_sources[0x30]	207591	1			T1	1		T3	53		T6	7
valid_sources[0x31]	215146	1			T3	70		T6	6		T9	755
valid_sources[0x32]	214084	1			T1	4		T3	60		T4	94
valid_sources[0x33]	330754	1			T1	4		T3	51		T6	4
valid_sources[0x34]	229483	1			T1	2		T3	38		T6	3
valid_sources[0x35]	207917	1			T1	3		T3	52		T6	4
valid_sources[0x36]	206602	1			T1	1		T3	64		T6	4
valid_sources[0x37]	241226	1			T1	2		T3	76		T6	3
valid_sources[0x38]	214270	1			T1	1		T3	47		T6	5
valid_sources[0x39]	227424	1			T1	2		T3	60		T6	7
valid_sources[0x3a]	240713	1			T3	81		T6	7		T7	1
valid_sources[0x3b]	210913	1			T1	4		T3	67		T6	4
valid_sources[0x3c]	198639	1			T1	6		T3	52		T6	7
valid_sources[0x3d]	207402	1			T1	1		T3	61		T6	3
valid_sources[0x3e]	207108	1			T1	3		T2	1188		T3	81
valid_sources[0x3f]	200607	1			T1	1		T3	79		T6	7
valid_sources[0x40]	220911	1			T3	81		T6	7		T9	761
valid_sources[0x41]	190010	1			T3	32		T6	7		T9	754
valid_sources[0x42]	217515	1			T2	2715		T3	47		T4	141
valid_sources[0x43]	200700	1			T3	46		T6	4		T7	2
valid_sources[0x44]	566007	1			T2	8551		T3	69		T6	4
valid_sources[0x45]	218296	1			T1	2		T3	33		T6	3
valid_sources[0x46]	198479	1			T1	6		T3	56		T6	3
valid_sources[0x47]	240085	1			T1	1		T3	72		T6	5
valid_sources[0x48]	208257	1			T1	1		T3	54		T6	7
valid_sources[0x49]	308061	1			T1	1		T3	58		T4	208
valid_sources[0x4a]	202518	1			T1	1		T3	83		T6	8
valid_sources[0x4b]	208397	1			T1	2		T3	66		T6	2
valid_sources[0x4c]	213416	1			T1	2		T3	61		T4	158
valid_sources[0x4d]	202881	1			T1	1		T3	73		T6	9
valid_sources[0x4e]	202981	1			T1	6		T3	53		T6	7
valid_sources[0x4f]	195504	1			T1	2		T3	64		T6	4
valid_sources[0x50]	203480	1			T3	63		T6	3		T9	738
valid_sources[0x51]	191079	1			T1	1		T3	52		T4	188
valid_sources[0x52]	204921	1			T1	2		T3	42		T6	1
valid_sources[0x53]	222211	1			T3	109		T6	4		T7	4
valid_sources[0x54]	206477	1			T1	1		T3	35		T6	6
valid_sources[0x55]	212640	1			T3	66		T6	3		T7	3
valid_sources[0x56]	205995	1			T1	2		T3	51		T6	7
valid_sources[0x57]	250786	1			T1	2		T3	72		T6	6
valid_sources[0x58]	197870	1			T1	3		T3	50		T6	5
valid_sources[0x59]	211718	1			T1	1		T3	34		T4	334
valid_sources[0x5a]	217472	1			T3	44		T6	10		T7	2
valid_sources[0x5b]	213061	1			T3	39		T4	188		T6	6
valid_sources[0x5c]	301896	1			T1	2		T3	64		T6	3
valid_sources[0x5d]	222965	1			T2	3325		T3	66		T6	12
valid_sources[0x5e]	199641	1			T1	3		T3	53		T4	564
valid_sources[0x5f]	209406	1			T1	3		T3	43		T6	6
valid_sources[0x60]	204208	1			T1	3		T3	41		T6	7
valid_sources[0x61]	201380	1			T1	1		T3	46		T4	49
valid_sources[0x62]	238958	1			T1	3		T3	55		T6	6
valid_sources[0x63]	205409	1			T3	52		T6	5		T7	1
valid_sources[0x64]	219226	1			T1	2		T3	57		T6	3
valid_sources[0x65]	205876	1			T3	59		T6	3		T7	5
valid_sources[0x66]	540974	1			T1	2		T3	37		T6	7
valid_sources[0x67]	215600	1			T1	1		T3	33		T4	224
valid_sources[0x68]	227133	1			T1	3		T3	39		T4	373
valid_sources[0x69]	215566	1			T1	1		T3	65		T6	4
valid_sources[0x6a]	196243	1			T1	2		T3	55		T6	10
valid_sources[0x6b]	239450	1			T1	1		T3	63		T6	4
valid_sources[0x6c]	195500	1			T1	1		T3	53		T6	7
valid_sources[0x6d]	222254	1			T1	1		T3	82		T6	4
valid_sources[0x6e]	226472	1			T1	1		T3	59		T6	5
valid_sources[0x6f]	221063	1			T1	3		T3	64		T6	5
valid_sources[0x70]	201266	1			T1	3		T3	75		T6	3
valid_sources[0x71]	207394	1			T1	2		T3	89		T4	158
valid_sources[0x72]	268624	1			T3	69		T6	3		T7	6
valid_sources[0x73]	200653	1			T3	60		T6	4		T7	3
valid_sources[0x74]	207329	1			T1	1		T3	62		T6	5
valid_sources[0x75]	201021	1			T1	1		T3	66		T6	6
valid_sources[0x76]	227808	1			T1	2		T3	32		T6	6
valid_sources[0x77]	257224	1			T1	2		T3	56		T6	5
valid_sources[0x78]	252045	1			T1	1		T3	70		T6	5
valid_sources[0x79]	212581	1			T1	1		T3	62		T6	7
valid_sources[0x7a]	216374	1			T1	6		T3	49		T6	3
valid_sources[0x7b]	207933	1			T1	1		T3	42		T4	134
valid_sources[0x7c]	214431	1			T3	65		T4	340		T6	8
valid_sources[0x7d]	225434	1			T1	1		T3	63		T6	3
valid_sources[0x7e]	205133	1			T1	3		T3	70		T6	5
valid_sources[0x7f]	223277	1			T1	1		T3	48		T6	5
valid_sources[0x80]	217312	1			T3	43		T6	13		T7	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10742608

1

T1

9

T2

137

T3

25

values[0x0]

all_enables

biggest_size

251190

1

T1

41

T2

41

T3

87

values[0x1]

all_enables

biggest_size

175029

1

T1

18

T2

26

T3

51