Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	447820057	0	0	0
ctrl_rd_A	447820057	1975	0	0
host_fifo_config_rd_A	447820057	5935	0	0
host_nack_handler_timeout_rd_A	447820057	1628	0	0
host_timeout_ctrl_rd_A	447820057	1478	0	0
intr_enable_rd_A	447820057	3536	0	0
ovrd_rd_A	447820057	2345	0	0
target_fifo_config_rd_A	447820057	1546	0	0
target_id_rd_A	447820057	1811	0	0
target_timeout_ctrl_rd_A	447820057	1680	0	0
timeout_ctrl_rd_A	447820057	1736	0	0
timing0_rd_A	447820057	1613	0	0
timing1_rd_A	447820057	1688	0	0
timing2_rd_A	447820057	1689	0	0
timing3_rd_A	447820057	1506	0	0
timing4_rd_A	447820057	1681	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1975	0	0
T87	7999	127	0	0
T88	3482	14	0	0
T89	3174	28	0	0
T90	2818	9	0	0
T91	32124	217	0	0
T92	54170	216	0	0
T93	8104	111	0	0
T94	2006	25	0	0
T95	2101	21	0	0
T96	5301	29	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	5935	0	0
T49	171307	204	0	0
T50	0	357	0	0
T80	244997	0	0	0
T97	0	338	0	0
T98	0	313	0	0
T99	0	169	0	0
T100	0	116	0	0
T101	0	105	0	0
T102	0	78	0	0
T103	0	198	0	0
T104	0	338	0	0
T105	214395	0	0	0
T106	189437	0	0	0
T107	787458	0	0	0
T108	28310	0	0	0
T109	964169	0	0	0
T110	132240	0	0	0
T111	436304	0	0	0
T112	22465	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1628	0	0
T87	7999	52	0	0
T88	3482	6	0	0
T89	3174	13	0	0
T90	2818	6	0	0
T91	32124	204	0	0
T92	54170	305	0	0
T93	8104	68	0	0
T94	2006	12	0	0
T95	2101	9	0	0
T113	2260	2	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1478	0	0
T87	7999	32	0	0
T88	3482	4	0	0
T89	3174	13	0	0
T90	2818	5	0	0
T91	32124	234	0	0
T92	54170	259	0	0
T93	8104	40	0	0
T94	2006	14	0	0
T95	2101	1	0	0
T113	2260	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	3536	0	0
T49	171307	11	0	0
T50	0	24	0	0
T80	244997	0	0	0
T97	0	14	0	0
T100	0	17	0	0
T101	0	28	0	0
T104	0	5	0	0
T105	214395	0	0	0
T106	189437	0	0	0
T107	787458	0	0	0
T108	28310	0	0	0
T109	964169	0	0	0
T110	132240	0	0	0
T111	436304	0	0	0
T112	22465	0	0	0
T114	0	35	0	0
T115	0	19	0	0
T116	0	56	0	0
T117	0	48	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	2345	0	0
T11	53240	0	0	0
T14	216713	0	0	0
T23	38051	0	0	0
T61	278771	0	0	0
T65	3145	58	0	0
T74	159652	0	0	0
T81	70341	0	0	0
T82	101621	0	0	0
T83	34295	0	0	0
T85	0	36	0	0
T118	0	75	0	0
T119	0	54	0	0
T120	0	41	0	0
T121	0	29	0	0
T122	0	55	0	0
T123	0	35	0	0
T124	0	84	0	0
T125	0	78	0	0
T126	75696	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1546	0	0
T87	7999	64	0	0
T88	3482	1	0	0
T89	3174	14	0	0
T90	2818	11	0	0
T91	32124	227	0	0
T92	54170	271	0	0
T93	8104	49	0	0
T94	2006	5	0	0
T95	2101	1	0	0
T96	5301	11	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1811	0	0
T87	7999	84	0	0
T88	3482	2	0	0
T89	3174	36	0	0
T90	2818	18	0	0
T91	32124	246	0	0
T92	54170	246	0	0
T93	8104	95	0	0
T94	2006	15	0	0
T95	2101	3	0	0
T113	2260	7	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1680	0	0
T87	7999	75	0	0
T88	3482	26	0	0
T89	3174	7	0	0
T90	2818	3	0	0
T91	32124	197	0	0
T92	54170	354	0	0
T93	8104	69	0	0
T94	2006	18	0	0
T95	2101	8	0	0
T113	2260	2	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1736	0	0
T87	7999	71	0	0
T88	3482	22	0	0
T89	3174	11	0	0
T90	2818	1	0	0
T91	32124	222	0	0
T92	54170	235	0	0
T93	8104	77	0	0
T94	2006	8	0	0
T96	5301	25	0	0
T113	2260	6	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1613	0	0
T87	7999	55	0	0
T88	3482	16	0	0
T89	3174	8	0	0
T90	2818	7	0	0
T91	32124	211	0	0
T92	54170	314	0	0
T93	8104	71	0	0
T94	2006	8	0	0
T95	2101	8	0	0
T96	5301	16	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1688	0	0
T87	7999	52	0	0
T89	3174	11	0	0
T90	2818	12	0	0
T91	32124	211	0	0
T92	54170	324	0	0
T93	8104	70	0	0
T94	2006	8	0	0
T96	5301	51	0	0
T127	4789	7	0	0
T128	13214	218	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1689	0	0
T87	7999	38	0	0
T88	3482	9	0	0
T89	3174	23	0	0
T90	2818	15	0	0
T91	32124	241	0	0
T92	54170	275	0	0
T93	8104	54	0	0
T94	2006	1	0	0
T96	5301	39	0	0
T113	2260	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1506	0	0
T87	7999	36	0	0
T88	3482	20	0	0
T89	3174	7	0	0
T90	2818	7	0	0
T91	32124	243	0	0
T92	54170	241	0	0
T93	8104	45	0	0
T94	2006	5	0	0
T96	5301	24	0	0
T113	2260	4	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447820057	1681	0	0
T87	7999	61	0	0
T88	3482	14	0	0
T89	3174	6	0	0
T90	2818	6	0	0
T91	32124	229	0	0
T92	54170	232	0	0
T93	8104	76	0	0
T94	2006	11	0	0
T95	2101	1	0	0
T113	2260	5	0	0