Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

158583

1

T2

240

T4

285

T5

10

ack

14668

1

T2

32

T4

7

T5

4

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	670	1			T9	2		T10	1		T31	2
high	35216	1			T2	37		T4	53		T5	6
med	64732	1			T2	104		T4	100		T5	4
sml	71903	1			T2	130		T4	136		T5	4
all_zero	730	1			T2	1		T4	3		T10	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86593

1

T2

149

T4

148

T5

9

auto[1]

86658

1

T2

123

T4

144

T5

5

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119057

1

T2

200

T4

190

T5

9

auto[1]

54194

1

T2

72

T4

102

T5

5

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165545

1

T2

257

T4

286

T5

11

auto[1]

7706

1

T2

15

T4

6

T5

3

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163350

1

T2

241

T4

286

T5

10

auto[1]

9901

1

T2

31

T4

6

T5

4

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164311

1

T2

242

T4

288

T5

12

auto[1]

8940

1

T2

30

T4

4

T5

2

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86593

1

T2

149

T4

148

T5

9

auto[1]

86658

1

T2

123

T4

144

T5

5

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119057

1

T2

200

T4

190

T5

9

auto[1]

54194

1

T2

72

T4

102

T5

5

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165545

1

T2

257

T4

286

T5

11

auto[1]

7706

1

T2

15

T4

6

T5

3

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163350

1

T2

241

T4

286

T5

10

auto[1]

9901

1

T2

31

T4

6

T5

4

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164311

1

T2

242

T4

288

T5

12

auto[1]

8940

1

T2

30

T4

4

T5

2

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T222

1

T223

1

T70

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T132

2

T224

1

T225

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

7

1

T54

1

T226

1

T227

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

288

1

T9

2

T228

1

T93

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

139

1

T2

1

T31

1

T81

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

127

1

T31

3

T81

1

T228

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

511

1

T2

2

T81

1

T228

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

248

1

T2

1

T9

2

T31

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

274

1

T81

4

T228

1

T42

9

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

495

1

T2

2

T9

3

T31

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

248

1

T2

2

T9

1

T31

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

231

1

T2

2

T81

1

T93

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T130

1

T199

1

T124

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T54

1

T229

1

T225

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T56

1

T230

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50615	1			T2	80		T4	88		T5	1
write_address_byte	9901	1			T2	31		T4	6		T5	4
read_with_ack	2257	1			T4	3		T5	2		T31	39
read_with_nack	5449	1			T2	15		T4	3		T5	1
stop_byte	8940	1			T2	30		T4	4		T5	2
write_address_byte_nak	4785	1			T2	24		T4	2		T5	1
data_byte_nack	158583	1			T2	240		T4	285		T5	10
stop_byte_nack	5243	1			T2	23		T4	2		T5	2
nakok_byte_nack	79257	1			T2	112		T4	143		T5	5
nakok_addr_byte_nack	2372	1			T2	13		T4	1		T9	5