Group : i2c_env_pkg::i2c_scl_sda_override_cg
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Group : i2c_env_pkg::i2c_scl_sda_override_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.scl_sda_override_cg 100.00 1 100 1 64 64



Group Instance : i2c_env_pkg.scl_sda_override_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance i2c_env_pkg.scl_sda_override_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance i2c_env_pkg.scl_sda_override_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_sclval 2 0 2 100.00 100 1 1 2
cp_sdaval 2 0 2 100.00 100 1 1 2
cp_txorvden 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.scl_sda_override_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cp_txorvden_x_sclval 4 0 4 100.00 100 1 1 0
cp_txorvden_x_sdaval 4 0 4 100.00 100 1 1 0


Summary for Variable cp_sclval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sclval

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 366 1 T79 10 T66 11 T82 10
auto[1] 369 1 T79 9 T66 9 T82 8


Summary for Variable cp_sdaval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sdaval

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 366 1 T79 8 T66 8 T82 14
auto[1] 369 1 T79 11 T66 12 T82 4


Summary for Variable cp_txorvden

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txorvden

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 359 1 T79 12 T66 10 T82 10
auto[1] 376 1 T79 7 T66 10 T82 8


Summary for Cross cp_txorvden_x_sclval

Samples crossed: cp_txorvden cp_sclval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sclval

Bins
cp_txorvden   cp_sclval   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 179 1 T79 7 T66 4 T82 6
auto[0] auto[1] 180 1 T79 5 T66 6 T82 4
auto[1] auto[0] 187 1 T79 3 T66 7 T82 4
auto[1] auto[1] 189 1 T79 4 T66 3 T82 4


Summary for Cross cp_txorvden_x_sdaval

Samples crossed: cp_txorvden cp_sdaval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sdaval

Bins
cp_txorvden   cp_sdaval   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 175 1 T79 6 T66 4 T82 7
auto[0] auto[1] 184 1 T79 6 T66 6 T82 3
auto[1] auto[0] 191 1 T79 2 T66 4 T82 7
auto[1] auto[1] 185 1 T79 5 T66 6 T82 1